Specifications

Data Structures
1.4 Per-CPU Database (CPU)
Table 1–4 (Cont.) Contents of Per-CPU Database
Field Name Contents
CPU$L_IPL_VEC* Vector recording, in inverse order, the IPLs of all spinlocks currently
held by the processor (that is, bit 0 represents IPL 31).
CPU$L_IPL_ARRAY* Array of 32 longwords, corresponding in inverse order to the 32 IPLs
(that is, the first longword represents IPL 31). Upon each successful
spinlock acquisition by this processor, the IPL vector corresponding to
the spinlock’s synchronization IPL (SPL$B_IPL) is incremented.
CPU$L_TPOINTER* Address of the sanity timer (CPU$W_SANITY_TIMER) of the active
processor with the next highest CPU ID.
CPU$W_SANITY_TIMER* Number of sanity cycles before this processor times out.
CPU$W_SANITY_TICKS* Number of clock ticks until the next sanity cycle.
CPU$L_VP_OWNER* PCB address of the vector consumer.
CPU$L_VP_VARIANT_EXIT* Variant exit address to the disabled fault handler.
CPU$L_VP_FLAGS* Vector processing flags. The following fields are defined within CPU$L_
VP_FLAGS:
CPU$V_VP_POWERFAIL Powerfail variant
CPU$V_VP_BUGCHECK Bugcheck variant
CPU$V_VP_CTX_INIT Initialization in progress for vector
context
CPU$V_VP_CTX_SAVE Save in progress for vector context
CPU$V_VP_CTX_RESTORE Restore in progress for vector
context
CPU$L_VP_CPUTIM* Scheduled time for a vector consumer.
CPU$B_FLAGS* Miscellaneous processor flags. The following fields are defined within
CPU$B_FLAGS:
CPU$V_SCHED Idle loop in wait for CPU scheduler
CPU$V_FOREVER STOP/CPU with /FOREVER qualifier
CPU$V_NEWPRIM Primary-to-be CPU
CPU$V_PSWITCH Live primary switch requested by primary
CPU
CPU$V_MMG_HELD CPU owns MMG spinlock
CPU$V_VBSS_TRAN VBSS transition in progress
CPU$L_INTFLAGS* Interlocked flags. This word contains one flag bit: CPU$V_STOPPING
for the CPU stopping indicator.
1–19