Specifications

Data Structures
1.5 Control Register Access Mailbox (CRAM)
1.5 Control Register Access Mailbox (CRAM)
The control register access mailbox (CRAM) holds information that describes
a mailbox I/O access of a control and status register of a device attached to
a remote bus. The CRAM contains information required by the software as
well as the hardware itself. For example, mailbox I/O transactions require
the physical address of the hardware mailbox, as well as the virtual address
of the corresponding mailbox pointer register (MBPR). Timeout values for the
transaction are also stored in the CRAM.
CRAMs are preallocated from system nonpaged memory. Once they have been
allocated, they are managed privately by the CRAM allocation and deallocation
routines (IOC$ALLOCATE_CRAM and IOC$DEALLOCATE_CRAM). Each
block of CRAMs begins with a structure known as a control register access
mailbox header (CRAMH). The blocks of CRAMs are maintained as a linked list
starting at system global location IOC$GQ_CRAMQ and linked through location
CRAM$L_FLINK of the CRAM.
The control register access mailbox is shown in Figure 1–6 and described in
Table 1–5.
1–20