Specifications

Data Structures
1.5 Control Register Access Mailbox (CRAM)
Table 1–5 Contents of Control Register Access Mailbox
Field Name Contents
CRAM$L_FLINK Forward link. Reserved for driver use.
CRAM$L_BLINK Backward link. Reserved for driver use.
CRAM$W_SIZE* CRAM structure size in bytes.
CRAM$B_TYPE* Structure type. Set to DYN$C_MISC when the CRAM is allocated.
CRAM$B_SUBTYPE* Structure subtype. Set to DYN$C_CRAM when the CRAM is allocated.
CRAM$L_MBPR* Address of mailbox pointer register (MBPR).
CRAM$Q_HW_MBX* Physical address of hardware mailbox structure at the end of the CRAM.
CRAM$Q_QUEUE_TIME Timeout value (in nanoseconds) for queuing mailbox operations. This
field is initialized to a default value, but can be changed by the driver.
CRAM$Q_WAIT_TIME Timeout value (in nanoseconds) for waiting for mailbox operation
completion. This field is initialized to a default value, but can be changed
by the driver.
CRAM$L_DRIVER This field is reserved for driver use.
CRAM$L_IDB* Address of Interrupt Dispatch Block (IDB).
CRAM$L_UCB* Address of Unit Control Block (UCB).
CRAM$B_CRAM_FLAGS CRAM flags. The only flag defined is CRAM$V_CRAM_IN_USE.
CRAM$L_CRAMHADDR* Virtual address of the CRAMH structure associated with this CRAM.
Hardware Mailbox Structure This 16-longword field (described in Section 1.5.1) is used by the
hardware to control the physical I/O operation.
1.5.1 Hardware Mailbox Structure
The hardware mailbox structure is part of the control register access mailbox
(CRAM), described in Section 1.5. This structure is used by the I/O processor
(IOP) hardware to perform the actual CSR access.
The hardware mailbox structure is shown in Figure 1–7 and described in
Table 1–6.
1–22