Specifications

Data Structures
1.5 Control Register Access Mailbox (CRAM)
Table 1–6 Contents of the Hardware Mailbox Structure
Field Name Contents
HW_CRAM$L_COMMAND Bus command to the remote I/O interconnect. Specifies either a read
or write transaction. The local I/O adapter delivers this command to
the remote interconnect to which the target device is connected. The
command may also include fields such as address width and data width.
HW_CRAM$B_MASK Active byte mask indicating which bytes within the remote bus address
are to be written. (The full name of this field is HW_CRAM$B_BYTE_
MASK.)
HW_CRAM$B_HOSE I/O bus (or hose) number specifying the remote I/O interconnect to be
accessed.
HW_CRAM$Q_RBADR Remote bus address specifying the physical address of the device interface
register.
HW_CRAM$Q_WDATA Data to be written.
HW_CRAM$Q_RDATA Returned read data.
HW_CRAM$W_MBX_FLAGS Flags bitmask. The following flags are defined:
HW_CRAM$V_MBX_DONE Mailbox operation has completed. This
bit, when set, indicates that any error
bits and the read data field are valid.
Note, however, it does not guarantee
that a remote write operation has
actually completed at the remote
device.
HW_CRAM$V_MBX_ERROR There was an error in the operation.
The CRAM$W_ERROR_BITS field
contains additional information.
HW_CRAM$W_ERROR_BITS Device-specific error bits.
1.6 Control Register Access Mailbox Header (CRAMH)
The control register access mailbox header (CRAMH) describes a block of control
register access mailboxes (CRAMs).
CRAMs are preallocated in a pool in nonpaged system memory, four pages at a
time. Each contiguous section of memory is divided into one header (CRAMH)
and 15 CRAMs. If a driver attempts to allocate a CRAM when there are none
available, another four-page section of nonpaged memory is allocated and divided
into one header and 15 CRAMs.
The control register access mailbox header is shown in Figure 1–8 and described
in Table 1–7.
1–24