Specifications

Data Structures
1.7 Channel Request Block (CRB)
Table 1–9 (Cont.) Contents of Interrupt Transfer Vector Block (VEC)
Field Name Contents
VEC$L_INTD* Interrupt dispatching code, written by the driver-loading procedure as
follows:
PUSHR #^M<R0,R1,R2,R3,R4,R5>
JSB @#
The destination of the JSB instruction is the driver’s interrupt service
routine, as indicated at offset VEC$L_ISR. Under normal operations, direct-
vector UNIBUS or Q22–bus adapters—as well as VAXBI system interrupt
dispatching—transfer control to CRB$L_INTD. The code located here causes
the processor to execute the PUSHR instruction to save R0 through R5 on
the stack and execute a JSB instruction to transfer control to the driver’s
interrupt service routine.
In dispatching interrupts from non-direct-vector UNIBUS adapters, the
UNIBUS adapter interrupt service routine transfers control to CRB$L_
INTD+2, which contains the JSB instruction to the driver’s interrupt service
routine. Because the UNIBUS adapter’s interrupt service routine has
already saved R0 through R5, interrupt dispatching bypasses the PUSHR
instruction in these instances.
This field, plus VEC$L_ISR, is also known as VEC$Q_DISPATCH.
VEC$L_ISR The DPT in every driver for an interrupting device specifies the address of a
driver interrupt service routine.
VEC$L_IDB* Address of IDB for controller. The driver-loading procedure creates an IDB
for each CRB and loads the address of the IDB in this field. Device drivers
use the IDB address to obtain the virtual addresses of device registers.
When a driver’s interrupt service routine gains control, the top of the stack
contains a pointer to this field.
VEC$L_INITIAL Address of controller initialization routine. If a device controller requires
initialization at driver-loading time and during recovery from a power
failure, the driver specifies a value for this field in the DPT.
The driver-loading procedure calls this routine each time the procedure loads
the driver. The power failure recovery procedure also calls this routine to
initialize a controller after a power failure.
VEC$W_MAPREG The following bits are defined within VEC$W_MAPREG:
VEC$V_MAPREG Number of first standard map register allocated
to the driver that owns controller data channel.
IOC$REQMAPREG writes this field when
the routine allocates a set of standard map
registers to a driver fork process for a DMA
transfer. IOC$RELMAPREG reads the field to
deallocate a set of map registers.
Device drivers read this field in calculating
the starting address of a UNIBUS or
MicroVAX/Q22–bus transfer.
VEC$V_MAPLOCK Map register set is permanently allocated
(when set).
VEC$B_NUMREG Number of UNIBUS adapter or MicroVAX Q22–bus standard map registers
allocated to driver. IOC$REQMAPREG writes this 15-bit field when the
routine allocates a set of standard map registers. IOC$RELMAPREG reads
this field to deallocate a set of standard map registers.
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