Introduction to Quartus II ® Version 5.0 ® Altera Corporation 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 www.altera.
Introduction to Quartus II Version 5.0 Revision 1 April 2005 P25-09235-04 Altera, the Altera logo, FastTrack, HardCopy, MAX, MAX+PLUS, MAX+PLUS II, MegaCore, MegaWizard, NativeLink, Nios, OpenCore, Quartus, Quartus II, the Quartus II logo, and SignalTap are registered trademarks of Altera Corporation in the United States and other countries.
Contents Preface ............................................................................................................................................. ix Documentation Conventions ....................................................................................................... xi Chapter 1: Design Flow ................................................................................................................. 1 Introduction..................................................................
TABLE OF CONTENTS Assigning Design Partitions in the Project Navigator ................................ 62 Assigning Design Partitions with the Design Partitions Window............ 63 Importing Assignments ................................................................................................. 64 Verifying Pin Assignments............................................................................................ 65 Chapter 4: Synthesis ..............................................................
TABLE OF CONTENTS Chapter 7: Simulation ................................................................................................................ 127 Introduction................................................................................................................... 128 Simulating Designs with EDA Tools ......................................................................... 129 Specifying EDA Simulation Tool Settings ..................................................
TABLE OF CONTENTS Specifying Power Analyzer Options ......................................................................... 176 Using the PowerPlay Early Power Estimator........................................................... 178 Chapter 11: Programming & Configuration ........................................................................... 181 Introduction...................................................................................................................
TABLE OF CONTENTS Chapter 16: Software Development ......................................................................................... 237 Introduction................................................................................................................... 238 Using the Software Builder in the Quartus II Software .......................................... 238 Specifying Software Build Settings ............................................................................
Preface The Altera® Quartus® II design software is the most comprehensive environment available for system-on-a-programmable-chip (SOPC) design. If you have primarily used the MAX+PLUS® II software, other design software, or ASIC design software in the past, and are thinking of making the switch to the Quartus II software, or if you are somewhat familiar with the Quartus II software but would like to gain a greater knowledge of its capabilities, this manual is for you.
Documentation Conventions The Introduction to Quartus® II manual uses the following conventions to make it easy for you to find and interpret information. Typographic Conventions Quartus II documentation uses the typographic conventions shown in the following table: Visual Cue Meaning Bold Initial Capitals Command names; dialog box, page, and tab titles; and button names are shown in bold, with initial capital letters. For example: Find Text command, Save As dialog box, and Start button.
DOCUMENTATION CONVENTIONS Terminology The following table shows terminology that is used throughout the Introduction to Quartus II manual: Term Meaning “click” Indicates a quick press and release of the left mouse button. “double-click” Indicates two clicks in rapid succession. “choose” Indicates that you need to use a mouse or key combination to start an action. “select” Indicates that you need to highlight text and/or objects or an option in a dialog box with a key combination or the mouse.
Chapter One Design Flow What’s in Chapter 1: Introduction Graphical User Interface Design Flow 2 3 EDA Tool Design Flow 10 Command-Line Design Flow 16 Design Methodologies & Design Planning 30 1
CHAPTER 1: DESIGN FLOW INTRODUCTION Introduction The Altera® Quartus® II design software provides a complete, multiplatform design environment that easily adapts to your specific design needs. It is a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus II software includes solutions for all phases of FPGA and CPLD design. See Figure 1 for an illustration of the Quartus II design flow. Figure 1.
CHAPTER 1: DESIGN FLOW GRAPHICAL USER INTERFACE DESIGN FLOW Graphical User Interface Design Flow You can use the Quartus II software to perform all stages of the design flow; it is a complete, easy-to-use, stand-alone solution. Figure 2 shows the features that the Quartus II graphical user interface provides for each stage of the design flow. Figure 2.
CHAPTER 1: DESIGN FLOW GRAPHICAL USER INTERFACE DESIGN FLOW Figure 3 shows the Quartus II graphical user interface as it appears when you first start the software. Figure 3. Quartus II Graphical User Interface The Quartus II software includes a modular Compiler.
CHAPTER 1: DESIGN FLOW GRAPHICAL USER INTERFACE DESIGN FLOW You can run all Compiler modules as part of a full compilation by choosing Start Compilation (Processing menu). You can also run each module individually by choosing Start (Processing menu) and then choosing the command for the module you want to start from the Start submenu. You can also run some of the Compiler modules incrementally. See “Top-Down Incremental Compilation Flow” on page 30 for more information.
CHAPTER 1: DESIGN FLOW GRAPHICAL USER INTERFACE DESIGN FLOW Table 1. Commands for Common Compiler Flows Flow Description Quartus II Command from Processing Menu Full compilation flow Performs a full compilation of the current design. Start Compilation command Compilation and simulation flow If the simulation mode is timing, flow performs a full compilation and then a simulation of the current design.
CHAPTER 1: DESIGN FLOW GRAPHICAL USER INTERFACE DESIGN FLOW MAX+PLUS II look and feel allows you to use the familiar MAX+PLUS II layout, commands, and icons to control functions of the Quartus II software. Figure 5 shows the Customize dialog box. Figure 5. Customize Dialog Box The Customize dialog box also allows you to choose whether you want the optional Quartus II or the MAX+PLUS II quick menus to display, and whether you want them on the right or left side of the menu bar.
CHAPTER 1: DESIGN FLOW GRAPHICAL USER INTERFACE DESIGN FLOW Figure 6. Quartus II and MAX+PLUS II Quick Menus Quartus II Quick Menu MAX+PLUS II Quick Menu f For Information About Refer To Using the Quartus II design flow for MAX+PLUS II users “Quartus II Design Flow for MAX+PLUS II Users” in the Quartus II Handbook, vol.
CHAPTER 1: DESIGN FLOW GRAPHICAL USER INTERFACE DESIGN FLOW f For Information About Refer To Customizing the user interface “Overview: Working With the User Interface” and “Customizing the User Interface” in Quartus II Help Using the MAX+PLUS II look and feel “MAX+PLUS II Quick Start Guide for the Quartus II Software” and “List of MAX+PLUS II Commands” in Quartus II Help The following steps describe the basic design flow for using the Quartus II graphical user interface: 1.
CHAPTER 1: DESIGN FLOW EDA TOOL DESIGN FLOW 9. (Optional) Perform functional simulation on the design by using the Simulator and the Generate Functional Simulation Netlist command. 10. Perform place and route on the design by using the Fitter. 11. Perform a power estimation and analysis by using the PowerPlay Power Analyzer. 12. Perform timing analysis on the design by using the Timing Analyzer. 13. Perform timing simulation on the design by using the Simulator. 14.
CHAPTER 1: DESIGN FLOW EDA TOOL DESIGN FLOW Figure 7. EDA Tool Design Flow Source design files, including VHDL Design Files (.vhd) & Verilog Design Files (.v) Quartus II Analysis & Synthesis EDA Synthesis Tool EDA Physical Synthesis Tool Quartus II Fitter EDIF netlist files (.edf) or Verilog Quartus Mapping Files (.
CHAPTER 1: DESIGN FLOW EDA TOOL DESIGN FLOW Table 2.
CHAPTER 1: DESIGN FLOW EDA TOOL DESIGN FLOW Table 2. EDA Tools Supported by the Quartus II Software (Part 2 of 2) Function Physical Synthesis Supported EDA Tools NativeLink Support Magma Design Automation PALACE v Synplicity Amplify The EDA Tool Settings page of the Settings dialog box (Assignments menu) allows you to specify which EDA tools you want to use with the Quartus II software. See Figure 8. Figure 8.
CHAPTER 1: DESIGN FLOW EDA TOOL DESIGN FLOW The individual pages under EDA Tool Settings provide additional options for each type of EDA tool. The following steps describe the basic design flow for using other EDA tools with the Quartus II software. Refer to Table 2 on page 12 for a list of the supported EDA tools. 14 ■ 1. Create a new project and specify a target device or device family. 2. Create a Verilog HDL or VHDL design file by using a standard text editor.
CHAPTER 1: DESIGN FLOW EDA TOOL DESIGN FLOW 7. (Optional) Perform timing analysis on your design by using one of the Quartus II–supported EDA timing analysis tools. 8. (Optional) Perform timing simulation on your design by using one of the Quartus II–supported EDA simulation tools. 9. (Optional) Perform board-level verification by using one of the Quartus II–supported EDA board-level verification tools. 10.
CHAPTER 1: DESIGN FLOW COMMAND-LINE DESIGN FLOW f For Information About Refer To Using the Quartus II software with Synopsis PrimeTime software “Synopsys PrimeTime Support” in the Quartus II Handbook, vol. 3, on the Altera web site Using the Quartus II software with Cadence Encounter Conformal software “Cadence Encounter Conformal Equivalency Checker Support” in the Quartus II Handbook, vol.
CHAPTER 1: DESIGN FLOW COMMAND-LINE DESIGN FLOW Figure 9. Command-Line Design Flow Quartus II Shell quartus_sh The Quartus II Shell can be used as a Tcl interpreter for the Quartus II executables Source design files, including Verilog Design Files (.v), VHDL Design Files (.vhd), Verilog Quartus Mapping Files (.vqm), Text Design Files (.tdf), Block Design Files (.bdf) & EDIF netlist files (.
CHAPTER 1: DESIGN FLOW COMMAND-LINE DESIGN FLOW [ ! Stand-Alone Graphical User Interface Executables The Quartus II software also provides some stand-alone graphical user interface (GUI) executables. The qmegawiz executable provides a stand-alone GUI version of the MegaWizard Plug-In Manager, the quartus_pgmw executable provides a stand-alone GUI for the Programmer, and the quartus_stpw executable provides a stand-alone GUI for the SignalTap II Logic Analyzer. Table 3.
CHAPTER 1: DESIGN FLOW COMMAND-LINE DESIGN FLOW Table 3. Command-Line Executables (Part 2 of 2) Executable Name Title Function quartus_cdb Compiler Database Interface (including VQM Writer) Generates internal netlist files, including VQM Files, for the Quartus II Compiler database so they can be used for back-annotation and for the LogicLock feature, and back-annotates device and resource assignments to preserve the fit for future compilations.
CHAPTER 1: DESIGN FLOW COMMAND-LINE DESIGN FLOW ! Getting Help On the Quartus II Executables If you want to get help on the command-line options that are available for each of the Quartus II executables, type one of the following commands at the command prompt: -h r --help r --help= r You can also get help on command-line executables by using the Quartus II Command-Line Executable and Tcl API Help Browser, which is a Tcl- and T
CHAPTER 1: DESIGN FLOW COMMAND-LINE DESIGN FLOW For example, if you want to run the quartus_map executable for the chiptrip project, you could type the following command at the command prompt: quartus_map chiptrip r The quartus_map executable will perform analysis and synthesis and will produce a report file with the name chiptrip.map.rpt.
CHAPTER 1: DESIGN FLOW COMMAND-LINE DESIGN FLOW Table 4. Command-Line Compiler Flows (Part 2 of 2) Command-Line Option for quartus_sh --flow or execute_flow Flow Description Attempt Similar Placement flow Performs a full compilation on a previously compiled design where the Fitter compares the netlist and placement from the previous and current compilations. The Fitter compares the compilations in order to use as many node placements from the previous compilation as possible in the current compilation.
CHAPTER 1: DESIGN FLOW COMMAND-LINE DESIGN FLOW Using Standard Command-Line Commands & Scripts You can use the Quartus II executables with any command-line scripting method, such as Perl scripts, batch files, and Tcl scripts. These scripts can be designed to create new projects or to compile existing projects. You can also run the executables from the command prompt or console. Figure 10 shows an example of a standard command-line script.
CHAPTER 1: DESIGN FLOW COMMAND-LINE DESIGN FLOW Figure 11 shows an excerpt from a sample command-line script for use on a UNIX workstation. The script assumes that the Quartus II tutorial project called fir_filter exists in the current directory. The script analyzes every design file in the fir_filter project and reports any files that contain syntax errors. Figure 11. Example of a UNIX Command-Line Shell Script #!/bin/sh FILES_WITH_ERRORS="" for filename in `ls *.bdf *.
CHAPTER 1: DESIGN FLOW COMMAND-LINE DESIGN FLOW ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Project & assignment functions Device functions Advanced device functions Flow functions Timing functions Advanced timing functions Simulator functions Report functions Timing report functions Back-annotate functions LogicLock functions Chip Editor functions Miscellaneous functions There are several ways to use Tcl scripts in the Quartus II software. You can create a Tcl script by using commands from the Quartus II API for Tcl.
CHAPTER 1: DESIGN FLOW COMMAND-LINE DESIGN FLOW Figure 12 shows an example of a Tcl script. Figure 12.
CHAPTER 1: DESIGN FLOW COMMAND-LINE DESIGN FLOW Figure 12. Example of a Tcl Script (Part 2 of 2) #------ Make a clock assignment with the Fmax requirement ------# create_base_clock clock -fmax $required_fmax #------ Make global assignments ------# set_global_assignment -name family STRATIX set_global_assignment -name device EP1S10F484C5 set_global_assignment -name tsu_requirement 7.
CHAPTER 1: DESIGN FLOW COMMAND-LINE DESIGN FLOW Figure 13. Excerpt from Makefile Script (Part 1 of 2) ################################################################### # Project Configuration: # # Specify the name of the design (project) and Quartus II Settings # File (.qsf) and the list of source files used. ################################################################### PROJECT = chiptrip SOURCE_FILES = auto_max.v chiptrip.v speed_ch.v tick_cnt.v time_cnt.v ASSIGNMENT_FILES = chiptrip.qpf chiptrip.
CHAPTER 1: DESIGN FLOW COMMAND-LINE DESIGN FLOW Figure 13. Excerpt from Makefile Script (Part 2 of 2) $(PROJECT).fit.rpt: fit.chg $(PROJECT).map.rpt quartus_fit $(FIT_ARGS) $(PROJECT) $(STAMP) asm.chg $(STAMP) tan.chg $(PROJECT).asm.rpt: asm.chg $(PROJECT).fit.rpt quartus_asm $(ASM_ARGS) $(PROJECT) $(PROJECT).tan.rpt: tan.chg $(PROJECT).fit.rpt quartus_tan $(TAN_ARGS) $(PROJECT) smart.log: $(ASSIGNMENT_FILES) quartus_sh --determine_smart_action $(PROJECT) > smart.
CHAPTER 1: DESIGN FLOW DESIGN METHODOLOGIES & DESIGN PLANNING Design Methodologies & Design Planning When you are creating a new design, it is important to consider the design methodologies the Quartus II software offers. For example, the LogicLock feature offers the ability to use top-down or bottom-up design methodologies, top-down incremental compilation design flows, and blockbased design flows. You can use these design flows with or without EDA design entry and synthesis tools.
CHAPTER 1: DESIGN FLOW DESIGN METHODOLOGIES & DESIGN PLANNING In the incremental compilation flow, you assign an instance of a design entity to a design partition. You then assign the partitions to a physical location on the device by using the Timing Closure Floorplan and the LogicLock feature, and perform a full compilation of the design. During compilation, the Compiler saves synthesis and fitting results in the project database.
CHAPTER 1: DESIGN FLOW DESIGN METHODOLOGIES & DESIGN PLANNING f For Information About Refer To Using Quartus II incremental compilation and incremental synthesis and the incremental compilation flow “Quartus II Incremental Compilation,” in the Quartus II Handbook, vol.
Chapter Two Design Entry What’s in Chapter 2: Introduction 34 Creating a Project 35 Creating a Design 43 Using Altera Megafunctions 47 2
CHAPTER 2: DESIGN ENTRY INTRODUCTION Introduction A Quartus® II project includes all of the design files, software source files, and other related files necessary for the successful operation of a design. Using revisions allows you to compare multiple versions of settings and assignments for your project, giving you the ability to meet design requirements more quickly and efficiently.
CHAPTER 2: DESIGN ENTRY CREATING A PROJECT Creating a Project You can create a new project by using the New Project Wizard (File menu) or the quartus_map executable. When creating a new project, you specify the working directory for the project, assign the project name, and designate the name of the top-level design entity.
CHAPTER 2: DESIGN ENTRY CREATING A PROJECT The Project Navigator displays information related to the current revision and provides a graphical representation of the project hierarchy, files, and design units, and shortcuts to various menu commands. You can also customize the information shown in the Project Navigator with the Customize Columns command (right button pop-up menu). Figure 2. Project Navigator Window The Project Navigator Window also allows you to assign design partitions.
CHAPTER 2: DESIGN ENTRY CREATING A PROJECT Using Revisions You can use revisions to specify, save, and use different groups of settings and assignments for the design files in a design. Revisions allow you to compare results using different settings and assignments for the same design files in a design. When you create a revision, the Quartus II software creates a separate QSF, which contains all the settings and assignments related to that revision, and places it in the top-level directory for the design.
CHAPTER 2: DESIGN ENTRY CREATING A PROJECT Figure 3. Revisions Dialog Box Creating a revision does not affect the source design files for the project. You can create a revision, set it as the current revision for the design, and then make assignments and settings for the entity. This feature allows you to create different settings and assignments for the same design entity and save those settings as different revisions for comparison.
CHAPTER 2: DESIGN ENTRY CREATING A PROJECT revisions you want to display and adjusting the order. You can also export a Comma-Separated Values File (.csv) from the comparison. Figure 4 shows the Results tab of the Compare Revisions dialog box, which allows you to compare the results of each revision. Figure 4. Results Tab of Compare Revisions Dialog Box Figure 5 shows the Assignments tab of the Compare Revisions dialog box, which allows you to compare the assignment settings for each revision.
CHAPTER 2: DESIGN ENTRY CREATING A PROJECT Figure 5. Assignments Tab of Compare Revisions Dialog Box f 40 ■ For Information About Refer To Using revisions “Quartus II Project Management,” in the Quartus II Handbook, vol.
CHAPTER 2: DESIGN ENTRY CREATING A PROJECT Using Version-Compatible Databases The Quartus II software allows you to export version-compatible database files for use in a later version of the Quartus II software, eliminating the need for a full compilation of the design in the later version of the Quartus II software. You can export a database at any stage in the design flow, after running Analysis & Synthesis or the quartus_map executable.
CHAPTER 2: DESIGN ENTRY CREATING A PROJECT f For Information About Refer To Using version-compatible databases “Quartus II Project Management,” in the Quartus II Handbook, vol. 2, on the Altera web site Converting MAX+PLUS II Projects The Convert MAX+PLUS II Project command (File menu) allows you to select an existing MAX+PLUS II project’s Assignment & Configuration File (.
CHAPTER 2: DESIGN ENTRY CREATING A DESIGN Creating a Design You can use the Quartus II software to create a design in the Quartus II Block Editor or use the Quartus II Text Editor to create an HDL design using the AHDL, Verilog HDL, or VHDL design languages. The Quartus II software also supports designs created from EDIF Input Files (.edf) or Verilog Quartus Mapping Files (.vqm) generated by EDA design entry and synthesis tools.
CHAPTER 2: DESIGN ENTRY CREATING A DESIGN Using the Quartus II Block Editor The Block Editor allows you to enter and edit graphic design information in the form of schematics and block diagrams. The Quartus II Block Editor reads and edits Block Design Files and MAX+PLUS II Graphic Design Files. You can open Graphic Design Files in the Quartus II software and save them as Block Design Files. The Block Editor is similar to the Graphic Editor from the MAX+PLUS II software.
CHAPTER 2: DESIGN ENTRY CREATING A DESIGN The Quartus II software provides symbols for a variety of logic functions—including primitives, library of parameterized modules (LPM) functions, and other megafunctions—that you can use in the Block Editor.
CHAPTER 2: DESIGN ENTRY CREATING A DESIGN Using Verilog HDL, VHDL & AHDL You can use the Quartus II Text Editor or another text editor to create Text Design Files, Verilog Design Files, and VHDL Design Files, and combine them with other types of design files in a hierarchical design. Verilog Design Files and VHDL Design Files can contain any combination of Quartus II–supported constructs.
CHAPTER 2: DESIGN ENTRY USING ALTERA MEGAFUNCTIONS Using Altera Megafunctions Altera megafunctions are complex or high-level building blocks that can be used together with gate and flipflop primitives in Quartus II design files. The parameterizable megafunctions and LPM functions provided by Altera are optimized for Altera device architectures. You must use megafunctions to access some Altera device-specific features, such as memory, DSP blocks, LVDS drivers, PLLs, and SERDES and DDIO circuitry.
CHAPTER 2: DESIGN ENTRY USING ALTERA MEGAFUNCTIONS f For Information About Refer To Using the MegaWizard Plug-In Manager “Overview: Using the MegaWizard Plug-In Manager” in Quartus II Help Design Entry module in the Quartus II Tutorial Using Intellectual Property (IP) Megafunctions Altera provides several methods for obtaining both Altera Megafunction Partners Program (AMPP™) and MegaCore® megafunctions, functions that are rigorously tested and optimized for the highest performance in Altera device-sp
CHAPTER 2: DESIGN ENTRY USING ALTERA MEGAFUNCTIONS You can install MegaCore functions from the MegaCore IP Library CD-ROM either during or after installation of the Quartus II software. You can also download individual IP MegaCore functions from the Altera web site, via the IP MegaStore, and install them separately. You can also access MegaCore functions though the MegaWizard Portal Extension to the MegaWizard Plug-In Manager.
CHAPTER 2: DESIGN ENTRY USING ALTERA MEGAFUNCTIONS Table 4. Files Generated by the MegaWizard Plug-In Manager File Name Description
CHAPTER 2: DESIGN ENTRY USING ALTERA MEGAFUNCTIONS Altera recommends that you use the MegaWizard Plug-In Manager to instantiate megafunctions and create custom megafunction variations. The wizard provides a graphical interface for customizing and parameterizing megafunctions, and ensures that you set all megafunction parameters correctly. Instantiation in Verilog HDL & VHDL You can use the MegaWizard Plug-In Manager to create a megafunction or a custom megafunction variation.
CHAPTER 2: DESIGN ENTRY USING ALTERA MEGAFUNCTIONS Instantiating Megafunctions in EDA Tools You can use Altera-provided megafunctions, LPM functions, and IP functions in EDA design entry and synthesis tools. You can instantiate megafunctions in EDA tools by creating a black box for the function, by inference, or by using the clear box methodology. Using the Black Box Methodology You can use the MegaWizard Plug-In Manager to generate Verilog HDL or VHDL wrapper files for megafunctions.
CHAPTER 2: DESIGN ENTRY USING ALTERA MEGAFUNCTIONS Instantiation by Inference EDA synthesis tools automatically recognize certain types of HDL code and infer the appropriate megafunction.You can directly instantiate memory blocks (RAM and ROM), DSP blocks, shift registers, and some arithmetic components in Verilog HDL or VHDL code. The EDA tool then maps the logic to the appropriate Altera megafunction during synthesis.
CHAPTER 2: DESIGN ENTRY USING ALTERA MEGAFUNCTIONS f For Information About Refer To List of ports and parameters for a megafunction If you are using an IP function, refer to the IP documentation. For Altera megafunctions, refer to Quartus II Help. Using Altera-provided megafunctions and LPM functions in EDA tools “Overview: Creating & Instantiating AlteraProvided Functions in Other EDA Tools” in Quartus II Help “Synplicity Synplify and Synplify Pro Support,” in the Quartus II Handbook, vol.
Chapter Three Constraint Entry What’s in Chapter 3: Introduction 56 Using the Assignment Editor 57 Using the Pin Planner 59 Using the Settings Dialog Box 60 Assigning Design Partitions 62 Importing Assignments 64 Verifying Pin Assignments 65 3
CHAPTER 3: CONSTRAINT ENTRY INTRODUCTION Introduction Once you have created a project and your design, you can use the Quartus® II Settings dialog box (Assignments menu), Assignment Editor, Pin Planner, Design Partitions window, and Timing Closure floorplan to specify initial design constraints, such as pin assignments, device options, logic options, and timing constraints.
CHAPTER 3: CONSTRAINT ENTRY USING THE ASSIGNMENT EDITOR Using the Assignment Editor The Assignment Editor is the interface for creating and editing node and entity-level assignments in the Quartus II software. Assignments allow you to specify various options and settings for the logic in your design, including location, I/O standard, timing, logic option, parameter, simulation, and pin assignments.
CHAPTER 3: CONSTRAINT ENTRY USING THE ASSIGNMENT EDITOR shows all assignments created for the current project that are valid for the current device, but when you view individual assignment categories, the Assignment Editor displays only the assignments that are related to the specific category selected. Figure 2. The Quartus II Assignment Editor f For Information About Refer To Using the Assignment Editor “Assignment Editor,” in the Quartus II Handbook, vol.
CHAPTER 3: CONSTRAINT ENTRY USING THE PIN PLANNER Using the Pin Planner The Pin Planner, which is available from the Assignments menu, is a visual tool that provides another way for you to make assignments to pins and groups of pins. It includes a package view of the device with different colors and symbols that represent the different types of pins and additional symbols that represent I/O banks. The symbols used in the Pin Planner are very similar to the symbols used in device family data sheets.
CHAPTER 3: CONSTRAINT ENTRY USING THE SETTINGS DIALOG BOX or more pins from the Unassigned Pins table to available pin or I/O bank locations in the package diagram. In the Assigned Pins table, you can filter the node names, change the I/O standards, and specify options for reserved pins. In the Unassigned Pins table, you can change the node name and direction for user-added nodes. You can also specify options for reserved pins. If you want, you can also turn off the lists of assigned and unassigned pins.
CHAPTER 3: CONSTRAINT ENTRY USING THE SETTINGS DIALOG BOX f ■ Specify compilation process settings: options for smart compilation, preserving node names, running the Assembler during compilation, incremental compilation or incremental synthesis, saving node-level netlists, exporting version-compatible databases, displaying entity names, and enabling or disabling the OpenCore® Plus evaluation feature. Also provides options for generating an early timing estimate.
CHAPTER 3: CONSTRAINT ENTRY ASSIGNING DESIGN PARTITIONS Assigning Design Partitions If you want to use the incremental compilation or incremental synthesis features, you can designate separate hierarchical sections of your design as design partitions on which you can perform Analysis & Synthesis or a full compilation incrementally, without affecting the rest of the project.
CHAPTER 3: CONSTRAINT ENTRY ASSIGNING DESIGN PARTITIONS Assigning Design Partitions with the Design Partitions Window You can specify an entity as a design partition with the Design Partitions Window command (Assignments menu). Figure 4 shows the Design Partitions window. Figure 4.
CHAPTER 3: CONSTRAINT ENTRY IMPORTING ASSIGNMENTS You can specify the netlist type by selecting the type from the list in the Netlist Type column or by selecting the partition and choosing Properties (right button pop-up menu). If you want to make a LogicLock assignment for a partition, you can drag the partition from the Design Partitions window directly to the LogicLock Regions window or to a LogicLock region in the Timing Closure floorplan.
CHAPTER 3: CONSTRAINT ENTRY VERIFYING PIN ASSIGNMENTS Figure 5. Import Assignments Dialog Box You can use this command to import the MAX+PLUS II Assignment & Configuration File, which contains MAX+PLUS II project assignments and settings, into your Quartus II project. You can also use this command to import settings and assignments from other projects created in the Quartus II software into your current project.
CHAPTER 3: CONSTRAINT ENTRY VERIFYING PIN ASSIGNMENTS assignments, allowing you to create your final pin-out faster. You do not need design files to use this command, and can verify pin-outs before design compilation. f 66 ■ For Information About Refer To Importing Assignments “I/O Assignment Planning and Analysis,” in the Quartus II Handbook, vol.
Chapter Four Synthesis What’s in Chapter 4: Introduction 68 Using Quartus II Verilog HDL & VHDL Integrated Synthesis 69 Using Other EDA Synthesis Tools 72 Controlling Analysis & Synthesis 75 Using the Design Assistant to Check Design Reliability 79 Analyzing Synthesis Results with the RTL Viewer 80 Analyzing Synthesis Results with the Technology Map Viewer 84 Performing Incremental Synthesis 86 4
CHAPTER 4: SYNTHESIS INTRODUCTION Introduction You can use the Quartus® II Analysis & Synthesis module of the Compiler to analyze your design files and create the project database. Analysis & Synthesis uses Quartus II Integrated Synthesis to synthesize your Verilog Design Files (.v) or VHDL Design Files (.vhd). If you prefer, you can use other EDA synthesis tools to synthesize your Verilog HDL or VHDL design files, and then generate an EDIF netlist file (.edf) or a Verilog Quartus Mapping File (.
CHAPTER 4: SYNTHESIS USING QUARTUS II VERILOG HDL & VHDL INTEGRATED SYNTHESIS ! Using the quartus_map executable You can also run Analysis & Synthesis separately at the command prompt or in a script by using the quartus_map executable. The quartus_map executable will create a new project if it does not already exist. The quartus_map executable creates a separate text-based report file that can be viewed with any text editor.
CHAPTER 4: SYNTHESIS USING QUARTUS II VERILOG HDL & VHDL INTEGRATED SYNTHESIS Figure 2. Verilog HDL & VHDL Input Pages of Settings Dialog Box Verilog HDL Input Page VHDL Input Page Most Verilog HDL and VHDL designs will compile successfully in both Quartus II Integrated Synthesis and in other EDA synthesis tools.
CHAPTER 4: SYNTHESIS USING QUARTUS II VERILOG HDL & VHDL INTEGRATED SYNTHESIS “Instantiating Megafunctions in the Quartus II Software” on page 50 and “Instantiating Megafunctions in EDA Tools” on page 52 in Chapter 2, “Design Entry.” When you create your Verilog HDL and VHDL designs, you should add them to the project.
CHAPTER 4: SYNTHESIS USING OTHER EDA SYNTHESIS TOOLS The Messages window and the Messages section of the Report window display any messages Analysis & Synthesis generates. The Status window displays the time spent processing in Analysis & Synthesis during project compilation.
CHAPTER 4: SYNTHESIS USING OTHER EDA SYNTHESIS TOOLS Table 1. Quartus II–Supported EDA Synthesis Tools Synthesis Tool Name EDIF Netlist File (.edf) Verilog Quartus Mapping File (.
CHAPTER 4: SYNTHESIS USING OTHER EDA SYNTHESIS TOOLS Figure 3. EDA Tool Design Entry & Synthesis Page of Settings Dialog Box If you have specified an EDA synthesis tool in the Design Entry & Synthesis page, you can run that tool from within the Quartus II software by choosing Start > Start EDA Synthesis (Processing menu). Many EDA tools also allow you to run the Quartus II software from within that EDA tool’s graphical user interface. Refer to your EDA tool documentation for more information.
CHAPTER 4: SYNTHESIS CONTROLLING ANALYSIS & SYNTHESIS f For Information About Refer To Using Synplicity Synplify software “Synplicity Synplify and Synplify Pro Support” in the Quartus II Handbook, vol. 1, on the Altera web site Using Mentor Graphics LeonardoSpectrum software “Mentor Graphics LeonardoSpectrum Support” in the Quartus II Handbook, vol.
CHAPTER 4: SYNTHESIS CONTROLLING ANALYSIS & SYNTHESIS You can also specify attributes, which are sometimes known as pragmas or directives, that drive the synthesis process for a a specific design element. Some attributes are also available as Quartus II logic options.
CHAPTER 4: SYNTHESIS CONTROLLING ANALYSIS & SYNTHESIS Figure 4. Analysis & Synthesis Settings Page of Settings Dialog Box The Quartus II logic options that are available on the Analysis & Synthesis Settings page allow you to specify that the Compiler should optimize for speed or area, or perform a “balanced” optimization, which attempts to achieve the best combination of speed and area.
CHAPTER 4: SYNTHESIS CONTROLLING ANALYSIS & SYNTHESIS f For Information About Refer To Using Quartus II logic options to control synthesis “Logic Options,” “Creating, Editing, and Deleting Assignments,” and “Specifying Settings for Default Logic Options” in Quartus II Help Creating a logic option assignment Compilation module in the Quartus II Tutorial Using Quartus II synthesis options and logic options that affect synthesis “Quartus II Integrated Synthesis,” in the Quartus II Handbook, vol.
CHAPTER 4: SYNTHESIS USING THE DESIGN ASSISTANT TO CHECK DESIGN RELIABILITY Using the Design Assistant to Check Design Reliability The Quartus II Design Assistant allows you to check the reliability of your design, based on a set of design rules. The Design Assistant is especially useful for checking the reliability of a design before migrating it for HardCopy™ devices.
CHAPTER 4: SYNTHESIS ANALYZING SYNTHESIS RESULTS WITH THE RTL VIEWER ! Using the quartus_drc executable You can also run the Design Assistant separately at the command prompt or in a script by using the quartus_drc executable. You must run the Quartus II Fitter executable quartus_fit before running the Design Assistant. The quartus_drc executable creates a separate text-based report file that can be viewed with any text editor.
CHAPTER 4: SYNTHESIS ANALYZING SYNTHESIS RESULTS WITH THE RTL VIEWER you can display the RTL Viewer window by choosing RTL Viewer (Tools menu). In addition to the schematic view, the RTL Viewer has a hierarchy list, which lists the instances, primitives, pins, and nets for the entire design netlist. See Figure 6. Figure 6. RTL Viewer Window The RTL viewer displays the Analysis & Elaboration results for Verilog HDL or VHDL designs, and AHDL Text Design Files (.tdf), Block Design Files (.
CHAPTER 4: SYNTHESIS ANALYZING SYNTHESIS RESULTS WITH THE RTL VIEWER design file, the Timing Closure floorplan, Assignment Editor, Chip Editor, Resource Property Editor, or Technology Map Viewer, depending on which locations are available for that node. If a design is large, the RTL Viewer partitions it into multiple pages for display.
CHAPTER 4: SYNTHESIS ANALYZING SYNTHESIS RESULTS WITH THE RTL VIEWER The State Machine Viewer includes a schematic view and a transition table. See Figure 8. Figure 8. State Machine Viewer Window Schematic view Double circles indicate nodes that have connections to outside logic Transition table shows source and destination states and transition conditions When you select a cell in transition table, the corresponding state or transition is highlighted in the schematic view.
CHAPTER 4: SYNTHESIS ANALYZING SYNTHESIS RESULTS WITH THE TECHNOLOGY MAP VIEWER f For Information About Refer To Using the Quartus II RTL Viewer “Analyzing Designs with the Quartus II RTL Viewer and Technology Map Viewer” in the Quartus II Handbook, vol.
CHAPTER 4: SYNTHESIS ANALYZING SYNTHESIS RESULTS WITH THE TECHNOLOGY MAP VIEWER Figure 9. Technology Map Viewer Window In the Technology Map Viewer, you can select one or more items in the hierarchy list to highlight in the schematic view, and vice versa. The Technology Map Viewer allows you to navigate the view in much the same way as the RTL Viewer; see “Analyzing Synthesis Results with the RTL Viewer” on page 80.
CHAPTER 4: SYNTHESIS PERFORMING INCREMENTAL SYNTHESIS Performing Incremental Synthesis Incremental synthesis is part of the top-down incremental compilation flow. It allows you to specify entities in your design as design partitions on which you can perform Analysis & Synthesis incrementally, without affecting the rest of the project. For more information in the incremental compilation design flow, refer to “Top-Down Incremental Compilation Flow” on page 30 in Chapter 1, “Design Flow.
CHAPTER 4: SYNTHESIS PERFORMING INCREMENTAL SYNTHESIS 4. f Compile the project: v Perform a full compilation on the project. After the initial compilation, if you make additional changes to the project, you should recompile the project. When you recompile the project, the software synthesizes each changed partition separately and then automatically merges the partitions to create a flattened netlist.
Chapter Five Place & Route What’s in Chapter 5: Introduction 90 Performing a Full Incremental Compilation 92 Analyzing Fitting Results 93 Optimizing the Fit 99 Preserving Assignments through Back-Annotation 109 5
CHAPTER 5: PLACE & ROUTE INTRODUCTION Introduction The Quartus® II Fitter, which is also known as the PowerFit™ Fitter, performs place and route, which is also referred to as “fitting” in the Quartus II software. Using the database that has been created by Analysis & Synthesis, the Fitter matches the logic and timing requirements of the project with the available resources of a device.
CHAPTER 5: PLACE & ROUTE INTRODUCTION logic of a design, the Compiler uses all modules during processing. This option is similar to the MAX+PLUS® II Smart Recompile command (Processing menu). You can start a full compilation in the Quartus II software, which includes the Fitter module, or you can start the Fitter separately. You must run Analysis & Synthesis successfully before starting the Fitter separately.
CHAPTER 5: PLACE & ROUTE PERFORMING A FULL INCREMENTAL COMPILATION Performing a Full Incremental Compilation You can perform a full incremental compilation to preserve design performance and save compilation time by reusing previous compilation results and ensuring that only the parts of the design that have been modified need to be recompiled. Performing a full incremental compilation is part of the top-down incremental compilation flow.
CHAPTER 5: PLACE & ROUTE ANALYZING FITTING RESULTS f For Information About Refer To Using Quartus II incremental compilation “Quartus II Incremental Compilation,” in the Quartus II Handbook, vol. 1, on the Altera web site “Overview: Using Incremental Compilation” in Quartus II Help Analyzing Fitting Results The Quartus II software offers several tools to help you analyze the results of compilation and fitting. The Messages window and Report window provide fitting results information.
CHAPTER 5: PLACE & ROUTE ANALYZING FITTING RESULTS Figure 3. Messages Window Arrow buttons allow you to select next and previous messages Location list allows you to select from multiple locations Clicking the Locate button displays the selected location In the Messages window, you can choose Help from the right button popup menu to get Help on a particular message. By default, all message types are displayed in the Processing tab of the Messages window.
CHAPTER 5: PLACE & ROUTE ANALYZING FITTING RESULTS which locations are available for that message. You can also select a message and then select a location from the Message Location list and click Locate to locate to a specific location.
CHAPTER 5: PLACE & ROUTE ANALYZING FITTING RESULTS Figure 4. Fitter Section of the Report Window The Quartus II software automatically generates text and HTML versions of the Report window, depending on which options you specify in the Processing page of the Options dialog box.
CHAPTER 5: PLACE & ROUTE ANALYZING FITTING RESULTS editable Timing Closure floorplan allows you to view logic placement made by the Fitter and/or user assignments, make LogicLock™ region assignments, and view routing congestion. See Figure 5. Figure 5.
CHAPTER 5: PLACE & ROUTE ANALYZING FITTING RESULTS To edit assignments in the Timing Closure floorplan, you can click a resource assignment and drag it to a new location. While dragging a resource in the Timing Closure floorplan, you can use rubberbanding to display a visual representation of the number of routing resources affected by the move. You can view the routing congestion in a design, view routing delay information for paths, and view connection counts to specific nodes.
CHAPTER 5: PLACE & ROUTE OPTIMIZING THE FIT page of the Settings dialog box (Assignments menu) allows you to specify which design reliability guidelines to use when checking your design. For more information, refer to “Using the Design Assistant to Check Design Reliability” on page 79 in Chapter 4, “Synthesis.
CHAPTER 5: PLACE & ROUTE OPTIMIZING THE FIT The Timing Closure floorplan provides different views of the device and helps you make precise assignments to specific locations. You can also view equations and routing information, and demote assignments by dragging and dropping assignments to various regions in the Regions window.
CHAPTER 5: PLACE & ROUTE OPTIMIZING THE FIT Setting Physical Synthesis Optimization Options The Quartus II software allows you to set options for performing physical synthesis to optimize the netlist during fitting. You specify physical synthesis optimization options in the Physical Synthesis Optimizations page under Fitter Settings in the Settings dialog box (Assignments menu).
CHAPTER 5: PLACE & ROUTE OPTIMIZING THE FIT options to specify that the signal should be available throughout the device on a global routing path, specify that the Fitter should create parallel expander chains automatically, specify that the Fitter should automatically combine a register with a combinational function in the same logic cell, also known as “register packing,” or limit the length of carry chains, cascade chains, and parallel expander chains. .
CHAPTER 5: PLACE & ROUTE OPTIMIZING THE FIT Figure 6. Resource Optimization Advisor Summary Page The first page of the Resource Optimization Advisor summarizes the resource usage after compilation, and indicates possible problem areas.
CHAPTER 5: PLACE & ROUTE OPTIMIZING THE FIT Figure 7. Resource Optimization Advisor Recommendation Page Hierarchical list of recommendations— icons indicate potential problem areas Some recommendations include buttons that will provide more information about the design, such as this list. Clicking a link in the recommendations page opens the appropriate dialog box, page, or feature.
CHAPTER 5: PLACE & ROUTE OPTIMIZING THE FIT If you want to view recommendations for improving timing results, you can use the Timing Optimization Advisor. See “Using the Timing Optimization Advisor” on page 166 in Chapter 9, “Timing Closure.” Using the Design Space Explorer Another way to control Quartus II fitting is to use the Design Space Explorer (DSE) Tcl script, dse.tcl, which can help you optimize your design.
CHAPTER 5: PLACE & ROUTE OPTIMIZING THE FIT Figure 8. Settings Tab of Design Space Explorer DSE provides several exploration modes, which are listed under Exploration Settings in the DSE window: ■ ■ ■ Search for Best Area Search for Best Performance (allows you to specify an effort level) Advanced Search Selecting the Advanced Search option enables the Advanced tab, which allows you to specify additional options for exploration space, optimization goal, and search method.
CHAPTER 5: PLACE & ROUTE OPTIMIZING THE FIT Figure 9. Advanced Tab of Design Space Explorer After you have specified your exploration settings, you can use the Explore Space command (Processing menu) or button to start the exploration. You can see the results of the exploration on the Explore tab. Figure 10 shows the Explore tab. You can also view the exploration results in a text file form by using the View Last DSE Report for Project command (Processing menu) or button.
CHAPTER 5: PLACE & ROUTE OPTIMIZING THE FIT Figure 10.
CHAPTER 5: PLACE & ROUTE PRESERVING ASSIGNMENTS THROUGH BACK-ANNOTATION Many of the Exploration Space modes allow you to specify the degree of effort you want DSE to spend in fitting the design; however, increasing the effort level usually increases the compilation time. Custom exploration mode allows you to specify various parameters, options, and modes and then explore their effects on your design.
CHAPTER 5: PLACE & ROUTE PRESERVING ASSIGNMENTS THROUGH BACK-ANNOTATION and location of LogicLock regions. You can specify assignments to backannotate in the Back-Annotate Assignments dialog box (Assignments menu). The Back-Annotate Assignments dialog box allows you to select the type of back-annotation: Default type or Advanced type. See Figure 11. Figure 11.
CHAPTER 5: PLACE & ROUTE PRESERVING ASSIGNMENTS THROUGH BACK-ANNOTATION assignments. The Back-Annotate Assignments (Advanced type) dialog box allows you to do everything that the Default back-annotation type allows you to do, as well as back-annotate LogicLock regions, and optionally the nodes and routing within them. The Advanced back-annotation type also provides many options for filtering based on region, path, resource type, and so on, and allows you to use wildcards.
Chapter Six Block-Based Design What’s in Chapter 6: Introduction 114 Quartus II Block-Based Design Flow 114 Using LogicLock Regions 116 Using LogicLock Regions in TopDown Incremental Compilation Flows 119 Saving Intermediate Synthesis Results for Bottom-Up LogicLock Flows 120 Using LogicLock with EDA Tools 124 6
CHAPTER 6: BLOCK-BASED DESIGN INTRODUCTION Introduction The Quartus® II LogicLock™ feature enables a block-based design flow by allowing you to create modular designs, designing and optimizing each module separately before incorporating it into the top-level design. Incorporating each module into the top-level design does not affect the performance of the lower level modules, as long as each module has registered inputs and outputs.
CHAPTER 6: BLOCK-BASED DESIGN QUARTUS II BLOCK-BASED DESIGN FLOW ■ Incremental compilation flow: In the incremental compilation flow, you create and optimize a system, and then add future modules with little or no effect on the performance of the original system. ■ Team-based design flow: In the team-based design flow, you partition a design into separate modules, and instantiate and connect the modules in a top-level design.
CHAPTER 6: BLOCK-BASED DESIGN USING LOGICLOCK REGIONS Using LogicLock Regions A LogicLock region is defined by its size (height and width) and location on the device. You can specify the size and location of a region, or direct the Quartus II software to create them automatically. Table 1 lists the major properties of LogicLock regions that you can specify in the Quartus II software. Table 1.
CHAPTER 6: BLOCK-BASED DESIGN USING LOGICLOCK REGIONS You can create and modify LogicLock regions by using the Timing Closure floorplan, the LogicLock Regions Window command (Assignments menu), the Hierarchy tab of the Project Navigator, or by using Tcl scripts. All LogicLock attributes and constraint information (clock settings, pin assignments, and relative placement information) are stored in the Quartus II Settings File (.qsf) for the project.
CHAPTER 6: BLOCK-BASED DESIGN USING LOGICLOCK REGIONS Figure 3. LogicLock Region Properties Dialog Box After you have performed analysis and elaboration or a full compilation, the Quartus II software displays the hierarchy of the design in the Hierarchy tab of the Project Navigator. You can click any of the design entities in this view and create new LogicLock regions from them, or drag them into an existing LogicLock region in the Timing Closure floorplan.
CHAPTER 6: BLOCK-BASED DESIGN USING LOGICLOCK REGIONS IN TOP-DOWN INCREMENTAL COMPILATION FLOWS f For Information About Refer To Using LogicLock with the Quartus II software “LogicLock Design Methodology,” in the Quartus II Handbook, vol.
CHAPTER 6: BLOCK-BASED DESIGN SAVING INTERMEDIATE SYNTHESIS RESULTS FOR BOTTOM-UP LOGICLOCK FLOWS After the initial or setup compilation, Altera recommends that you set the Size to Fixed in order to yield better fMAX results. If device utilization is low, increasing the size of the LogicLock region may allow the Fitter additional flexibility in placement and may produce better final results.
CHAPTER 6: BLOCK-BASED DESIGN SAVING INTERMEDIATE SYNTHESIS RESULTS FOR BOTTOM-UP LOGICLOCK FLOWS ! Save Intermediate Synthesis Results Only for Bottom-Up LogicLock Design Flows You should save intermediate synthesis results to a VQM File only if you are using a bottom-up LogicLock design flow, and should not save them if you are using a topdown incremental compilation flow with LogicLock regions. The top-down incremental compilation flow saves synthesis and fitting results in the project database.
CHAPTER 6: BLOCK-BASED DESIGN SAVING INTERMEDIATE SYNTHESIS RESULTS FOR BOTTOM-UP LOGICLOCK FLOWS ! Using the quartus_cdb executable You can also save intermediate synthesis results as a VQM File, back-annotate assignments, and export and import LogicLock regions separately at the command prompt or in a script by using the quartus_cdb executable.
CHAPTER 6: BLOCK-BASED DESIGN SAVING INTERMEDIATE SYNTHESIS RESULTS FOR BOTTOM-UP LOGICLOCK FLOWS software exports the LogicLock region assignments for the entire design. You can specify subdesign entities to export in the Export assignments hierarchy path box. See Figure 4. Figure 4. Export Assignments Dialog Box When you import LogicLock region assignments, the Quartus II software traverses the compilation hierarchy, starting at the current compilation focus.
CHAPTER 6: BLOCK-BASED DESIGN USING LOGICLOCK WITH EDA TOOLS Figure 5. Import Assignments Dialog Box When importing LogicLock regions, you can click Advanced in the Import Assignments dialog box to specify the nature of the assignments to import, specify global or instance-level assignments to import, and specify how the assignments affect the current design. You can also create a backup of the current QSF for the design before importing assignments.
CHAPTER 6: BLOCK-BASED DESIGN USING LOGICLOCK WITH EDA TOOLS to place each netlist file or module within a netlist file into a separate LogicLock region in a top-level design. Once in the Quartus II software, you can make changes, optimize, and resynthesize specific modules in the design by using the EDA tool to update the corresponding part of the design, without affecting the other modules in the design.
Chapter Seven Simulation What’s in Chapter 7: Introduction 128 Simulating Designs with EDA Tools 129 Simulating Designs with the Quartus II Simulator 136 7
CHAPTER 7: SIMULATION INTRODUCTION Introduction You can perform functional and timing simulation of your design by using EDA simulation tools or the Quartus® II Simulator.
CHAPTER 7: SIMULATION SIMULATING DESIGNS WITH EDA TOOLS Simulating Designs with EDA Tools The EDA Netlist Writer module of the Quartus II software generates VHDL Output Files (.vho) and Verilog Output Files (.vo) for performing functional or timing simulation and Standard Delay Format Output Files (.sdo) that are required for performing timing simulation with EDA simulation tools. The Quartus II software generates SDF Output Files in Standard Delay Format version 2.1.
CHAPTER 7: SIMULATION SIMULATING DESIGNS WITH EDA TOOLS Specifying EDA Simulation Tool Settings You can select an EDA simulation tool in the New Project Wizard (File menu) when you create a new project, or in the Simulation page that is under EDA Tool Settings in the Settings dialog box (Assignments menu).
CHAPTER 7: SIMULATION SIMULATING DESIGNS WITH EDA TOOLS Generating Simulation Output Files You can run the EDA Netlist Writer module to generate Verilog Output Files and VHDL Output Files by specifying EDA tool settings and compiling the design.
CHAPTER 7: SIMULATION SIMULATING DESIGNS WITH EDA TOOLS top-level design file and test vectors from the Vector Waveform File. You can also generate self-checking test bench files if you specify the expected values in the Vector Waveform File. ■ Memory Initialization Files: You can use the Quartus II Memory Editor to enter the initial contents of a memory block, for example, content-addressable memory (CAM), RAM, or ROM, in a Memory Initialization File (.mif) or a Hexadecimal (Intel-Format) File (.hex).
CHAPTER 7: SIMULATION SIMULATING DESIGNS WITH EDA TOOLS 4. Compile the design files and test bench files with the EDA simulation tool. 5. Perform the simulation with the EDA simulation tool. NativeLink Simulation Flow You can use the NativeLink feature to perform the steps to setup and run an EDA simulation tool automatically from within the Quartus II software. The following steps describe the basic flow for using EDA simulation tools with the NativeLink feature: 1.
CHAPTER 7: SIMULATION SIMULATING DESIGNS WITH EDA TOOLS 2. Compile the design in the Quartus II software to generate the output netlist files. The Quartus II software places the files in a tool-specific directory. 3. Launch the EDA simulation tool. 4. Set up the project and a working directory with the EDA simulation tool. 5. Compile or map to the timing simulation libraries, and compile the design and test bench files with the EDA simulation tool. 6.
CHAPTER 7: SIMULATION SIMULATING DESIGNS WITH EDA TOOLS Table 2. Functional Simulation Libraries (Part 2 of 2) Library Name Description sgate.v sgate.vhd sgate_pack.vhd Simulation models for Altera-specific megafunctions and Intellectual Property functions stratixgx_mf.v stratixgx_mf.vhd Libraries that contain simulation models for Stratix GX designs that contain the altgxb megafunction. For Verilog designs, you must compile the 220model.v and sgate.
CHAPTER 7: SIMULATION SIMULATING DESIGNS WITH THE QUARTUS II SIMULATOR Simulating Designs with the Quartus II Simulator You can use the Quartus II Simulator to simulate any design in a project.
CHAPTER 7: SIMULATION SIMULATING DESIGNS WITH THE QUARTUS II SIMULATOR Figure 3. Simulator Page in Settings Dialog Box Before starting a simulation, you must generate the appropriate simulation netlist by either compiling the design for timing simulation or choosing the Generate Functional Simulation Netlist command (Processing menu) for functional simulation. In addition, you must create and specify a vector source file as the source of simulation input vectors.
CHAPTER 7: SIMULATION SIMULATING DESIGNS WITH THE QUARTUS II SIMULATOR The following steps describe the basic flow for performing either a functional or timing simulation in the Quartus II software: 1. Specify Simulator settings. 2. If you are performing a functional simulation, choose the Generate Functional Simulation Netlist command. If you are performing a timing simulation, compile the design. 3. Create and specify a vector source file. 4.
CHAPTER 7: SIMULATION SIMULATING DESIGNS WITH THE QUARTUS II SIMULATOR Figure 4. The Quartus II Waveform Editor The Quartus II software supports waveform files in the Vector Waveform File (.vwf), Vector Table Output File (.tbl), Vector File (.vec), and Simulator Channel File (.scf) formats. You cannot edit a Simulator Channel File or Vector File in the Waveform Editor, but you can save it as a Vector Waveform File.
CHAPTER 7: SIMULATION SIMULATING DESIGNS WITH THE QUARTUS II SIMULATOR Figure 5.
Chapter Eight Timing Analysis What’s in Chapter 8: Introduction 142 Performing Timing Analysis in the Quartus II Software 143 Performing an Early Timing Estimate 150 Viewing Timing Analysis Results 152 Performing Timing Analysis by Using EDA Tools 157 8
CHAPTER 8: TIMING ANALYSIS INTRODUCTION Introduction The Quartus® II Timing Analyzer allows you to analyze the performance of all logic in your design and helps to guide the Fitter to meet the timing requirements in your design.
CHAPTER 8: TIMING ANALYSIS PERFORMING TIMING ANALYSIS IN THE QUARTUS II SOFTWARE Performing Timing Analysis in the Quartus II Software The Timing Analyzer automatically performs timing analysis on your design during a full compilation.
CHAPTER 8: TIMING ANALYSIS PERFORMING TIMING ANALYSIS IN THE QUARTUS II SOFTWARE Figure 2. Timing Requirements & Options Page of Settings Dialog Box Clicking the More Settings button displays the More Timing Settings dialog box, which contains additional options You can make individual timing settings with the Assignment Editor.
CHAPTER 8: TIMING ANALYSIS PERFORMING TIMING ANALYSIS IN THE QUARTUS II SOFTWARE You can specify I/O timing requirements by including these paths as part of the clock analysis and using the Input Maximum Delay, Input Minimum Delay, Output Maximum Delay, or Output Minimum Delay assignments to specify delays based on external device timing, or you can specify I/O timing by using the traditional tSU requirement, tCO requirement, and/or tH requirement timing assignments.
CHAPTER 8: TIMING ANALYSIS PERFORMING TIMING ANALYSIS IN THE QUARTUS II SOFTWARE Table 1. Project-Wide Timing Settings (Part 2 of 2) Requirement Description tH (clock hold time) The length of time for which data that feeds a register via its data or enable input(s) must be retained at an input pin after the clock signal that clocks the register is asserted at the clock pin.
CHAPTER 8: TIMING ANALYSIS PERFORMING TIMING ANALYSIS IN THE QUARTUS II SOFTWARE ■ Clock uncertainty assignments: allow you to specify the expected clock setup or hold uncertainty (jitter) that should be used when performing setup and hold checks. The Timing Analyzer subtracts the specified setup uncertainty from the data required time when calculating setup checks and adds the specified hold uncertainty to the data required time when calculating hold checks.
CHAPTER 8: TIMING ANALYSIS PERFORMING TIMING ANALYSIS IN THE QUARTUS II SOFTWARE ■ Time group assignments: advanced timing assignments that you can define in the Time Groups dialog box (Assignments menu); you can also use the Tcl API in the Quartus II Tcl Console, or one of the Quartus II executables that support Tcl. Members of a defined time group can include regular node names, wildcards, and/or other time group names.
CHAPTER 8: TIMING ANALYSIS PERFORMING TIMING ANALYSIS IN THE QUARTUS II SOFTWARE Figure 3. Timing Analyzer Tool ! Using the quartus_tan executable You can also run the Timing Analyzer separately at the command prompt or in a script by using the quartus_tan executable. You must run the Quartus II Fitter executable quartus_fit before running the Timing Analyzer. The quartus_tan executable creates a separate text-based report file that can be viewed with any text editor.
CHAPTER 8: TIMING ANALYSIS PERFORMING AN EARLY TIMING ESTIMATE f For Information About Refer To Specific timing settings and performing a timing analysis in the Quartus II Software “Overview: Using the Timing Analyzer” in Quartus II Help “Quartus II Timing Analysis,” in the Quartus II Handbook, vol.
CHAPTER 8: TIMING ANALYSIS PERFORMING AN EARLY TIMING ESTIMATE Figure 4. Early Timing Estimate Page in the Settings Dialog Box When you run the Start> Start Early Timing Estimate command, the Compiler performs a partial compilation that includes Analysis & Synthesis but stops before the Fitter is complete.
CHAPTER 8: TIMING ANALYSIS VIEWING TIMING ANALYSIS RESULTS Viewing Timing Analysis Results After you run a timing analysis, you can view the timing analysis results or early timing estimates in the Timing Analyzer folder of the Compilation Report. You can then list the timing paths to validate circuit performance, determine critical speed paths and paths that limit the design’s performance, and make additional timing assignments.
CHAPTER 8: TIMING ANALYSIS VIEWING TIMING ANALYSIS RESULTS Figure 5. Timing Analysis Results in the Compilation Report Window If you want to generate timing results using both the fast (best-case) timing model and slow (worst-case) timing models, you can specify that the Timing Analyzer should analyze and report timing using both the fast and slow models, and display the results in separate sections under the Timing Analyzer Section.
CHAPTER 8: TIMING ANALYSIS VIEWING TIMING ANALYSIS RESULTS The following steps describe the basic flow for making individual timing assignments in the Assignment Editor: 1. In the Category bar, click Timing to indicate the category of assignment you wish to make. 2. Click the To cell in the spreadsheet and use the Node Finder to find a node, or type a node name, wildcard character, and/or time group name that identifies the destination node you want to assign. 3.
CHAPTER 8: TIMING ANALYSIS VIEWING TIMING ANALYSIS RESULTS Figure 6. Output from List Paths Command The list_path Tcl command, which you can use in the quartus_tan module and the Quartus II Tcl Console, allows you to specify any point-topoint path and view the delay information. You can specify the number of paths to report, the type of path (including minimum timing paths), and use wildcards to identify source and destination nodes.
CHAPTER 8: TIMING ANALYSIS VIEWING TIMING ANALYSIS RESULTS Using the Technology Map Viewer The Quartus II Technology Map Viewer provides a low-level, or atom-level, technology-specific schematic representation a design. The Technology Map Viewer includes a schematic view, and also includes a hierarchy list, which lists the instances, primitives, pins, and nets for the entire design netlist.
CHAPTER 8: TIMING ANALYSIS PERFORMING TIMING ANALYSIS BY USING EDA TOOLS f For Information About Refer To Using the Quartus II Technology Map Viewer “Analyzing Designs with the Quartus II RTL Viewer and Technology Map Viewer” in the Quartus II Handbook, vol.
CHAPTER 8: TIMING ANALYSIS PERFORMING TIMING ANALYSIS BY USING EDA TOOLS Figure 9. EDA Tool Timing Analysis Page of Settings Dialog Box You can also generate the files by using the Start > Start EDA Netlist Writer command (Processing menu) after an initial compilation. If you are using the NativeLink® feature, you can also run a timing analysis after an initial compilation by using the Run EDA Timing Analysis Tool command (Tools menu).
CHAPTER 8: TIMING ANALYSIS PERFORMING TIMING ANALYSIS BY USING EDA TOOLS ! Using the quartus_eda executable You can also run the EDA Netlist Writer to generate the necessary output files separately at the command prompt or in a script by using the quartus_eda executable. You must run the Quartus II Fitter executable quartus_fit before running the EDA Netlist Writer. The quartus_eda executable creates a separate text-based report file that can be viewed with any text editor.
CHAPTER 8: TIMING ANALYSIS PERFORMING TIMING ANALYSIS BY USING EDA TOOLS 3. Source the Quartus II-generated Tcl Script File (.tcl) to set up the PrimeTime environment. 4. Perform timing analysis in the PrimeTime software. Using the Tau Software The Quartus II software generates STAMP model files that can be imported into the Tau software to perform board-level timing verification. The following steps describe the basic flow for generating STAMP model files: f 160 ■ 1.
Chapter Nine Timing Closure What’s in Chapter 9: Introduction 162 Using the Timing Closure Floorplan 162 Using the Timing Optimization Advisor 166 Using Netlist Optimizations to Achieve Timing Closure 167 Using LogicLock Regions to Achieve Timing Closure 169 Using the Design Space Explorer to Achieve Timing Closure 172 9
CHAPTER 9: TIMING CLOSURE INTRODUCTION Introduction The Quartus® II software offers a fully integrated timing closure flow that allows you to meet your timing goals by controlling the synthesis and place and route of a design. Using the timing closure flow results in faster timing closure for complex designs, reduced optimization iterations, and automatic balancing of multiple design constraints.
CHAPTER 9: TIMING CLOSURE USING THE TIMING CLOSURE FLOORPLAN You can customize the way the Timing Closure floorplan displays information using options available from the View menu. You can show the device by package pins and their function; by interior MegaLAB™ structures, LABs, and cells; by regions of the chip; and by the name and location of selected signals.
CHAPTER 9: TIMING CLOSURE USING THE TIMING CLOSURE FLOORPLAN potential destination resources (the darker the resource, the longer the delay) and the delay to a destination resource is shown numerically by placing the mouse over another physical resource. ■ Routing congestion: displays a graphical representation of the routing congestion in a design. The darker the shading, the greater the routing resource utilization.
CHAPTER 9: TIMING CLOSURE USING THE TIMING CLOSURE FLOORPLAN nodes that feed the selected logic cell, embedded cell, and/or pin assignments. The Fan-Out list displays all nodes that are fed by the selected logic cell, embedded cell, and/or pin assignments. Making Assignments To facilitate achieving timing closure, the Timing Closure floorplan allows you to make or change location assignments directly in the floorplan.
CHAPTER 9: TIMING CLOSURE USING THE TIMING OPTIMIZATION ADVISOR f For Information About Refer To Working with assignments in the Floorplan Editor “Overview: Working with Assignments in the Floorplan Editor” in Quartus II Help LogicLock module in the Quartus II tutorial Using the Timing Optimization Advisor The Timing Optimization Advisor offers recommendations for optimizing your design for timing in the following areas: ■ ■ ■ ■ Maximum frequency (fMAX) Setup timing (tSU) Clock-to-output (tCO) Propag
CHAPTER 9: TIMING CLOSURE USING NETLIST OPTIMIZATIONS TO ACHIEVE TIMING CLOSURE The Timing Optimization Advisor features are very similar to the Resource Optimization Advisor; for more information, refer to “Using the Resource Optimization Advisor” on page 102 in Chapter 5, “Place & Route.” Using Netlist Optimizations to Achieve Timing Closure The Quartus II software includes netlist optimization options to further optimize your design during synthesis and during place and route.
CHAPTER 9: TIMING CLOSURE USING NETLIST OPTIMIZATIONS TO ACHIEVE TIMING CLOSURE Figure 4. Netlist Optimizations Synthesis Netlist Optimizations Physical Synthesis Optimizations ■ 168 ■ Allow register retiming to trade off Tsu/Tco with Fmax: Directs the Quartus II software to move logic across registers that are associated with I/O pins during register retiming to trade off tCO and tSU with fMAX. When you turn on this option, register retiming can affect registers that feed and are fed by I/O pins.
CHAPTER 9: TIMING CLOSURE USING LOGICLOCK REGIONS TO ACHIEVE TIMING CLOSURE Netlist optimizations for physical synthesis and fitting include the following options: ■ Perform physical synthesis for combinational logic: Directs the Quartus II software to try to increase performance by performing physical synthesis optimizations on combinational logic during fitting.
CHAPTER 9: TIMING CLOSURE USING LOGICLOCK REGIONS TO ACHIEVE TIMING CLOSURE of modules. You can use the LogicLock feature on individual nodes, for instance, by assigning the nodes along the critical path to a LogicLock region. Successfully improving performance by using LogicLock regions in a design requires a detailed understanding of the design’s critical paths.
CHAPTER 9: TIMING CLOSURE USING LOGICLOCK REGIONS TO ACHIEVE TIMING CLOSURE Figure 5. Paths Dialog Box f For Information About Refer To Achieving timing closure using the LogicLock methodology “Timing Closure Floorplan,” in the Quartus II Handbook, vol. 2, on the Altera web site “LogicLock Design Methodology,” in the Quartus II Handbook, vol.
CHAPTER 9: TIMING CLOSURE USING THE DESIGN SPACE EXPLORER TO ACHIEVE TIMING CLOSURE Using the Design Space Explorer to Achieve Timing Closure You can use the Design Space Explorer (DSE) Tcl script, dse.tcl, to optimize your design for timing. The DSE interface allows you to explore a range of Quartus II options and settings automatically to determine which settings should be used to obtain the best possible result for the project.
Chapter Ten Power Analysis What’s in Chapter 10: Introduction 174 Performing Power Analysis with the PowerPlay Power Analyzer 174 Specifying Power Analyzer Options 176 Using the PowerPlay Early Power Estimator 178 10
CHAPTER 10: POWER ANALYSIS INTRODUCTION Introduction The Quartus® II PowerPlay Power Analysis Tools provide an interface that allows you to estimate static and dynamic power consumption throughout the design cycle. The PowerPlay Power Analyzer performs postfitting power analysis and produces a power report that highlights, by block type and entity, the power consumed.
CHAPTER 10: POWER ANALYSIS PERFORMING POWER ANALYSIS WITH THE POWERPLAY POWER ANALYZER probabilities using user assignments in Quartus II user interface or in the Quartus II Settings File (.qsf). For some device families, the Quartus II software will fill in any missing signal activity information by analyzing the design topology and function. You can then start power analysis by clicking Start in the Power Analyzer Tool window — a status bar shows the processing time.
CHAPTER 10: POWER ANALYSIS SPECIFYING POWER ANALYZER OPTIONS ! Using the quartus_pow utility You can also run the PowerPlay Power Analyzer separately at the command prompt or in a script by using the quartus_pow executable. You must run the Quartus II Fitter, quartus_fit, successfully before running the PowerPlay Power Analyzer. The quartus_pow executable creates a separate text-based report file that can be viewed with any text editor.
CHAPTER 10: POWER ANALYSIS SPECIFYING POWER ANALYZER OPTIONS Figure 3. PowerPlay Power Analyzer Settings Page Depending on the target device family, you can also specify default operating conditions for power analysis. You can specify the junction temperature, cooling solution requirements, and device characteristics in the Operating Conditions page of the Settings dialog box. See Figure 4.
CHAPTER 10: POWER ANALYSIS USING THE POWERPLAY EARLY POWER ESTIMATOR Figure 4. Operating Conditions Page Using the PowerPlay Early Power Estimator You can calculate a Stratix™, Stratix II, Stratix GX, Cyclone™, or MAX® II device’s power using the Altera PowerPlay Early Power Estimator spreadsheet, which you can download from the Power Consumption section of the Altera web site at http://www.altera.com/support/devices/estimator/ pow-powerplay.html.
CHAPTER 10: POWER ANALYSIS USING THE POWERPLAY EARLY POWER ESTIMATOR a Microsoft Excel-based spreadsheet that is specific to the current device family. A macro in the spreadsheet calculates the power estimation and then provides a current (ICC) and power (P) estimation in the spreadsheet.
Chapter Eleven Programming & Configuration What’s in Chapter 11: Introduction 182 Programming One or More Devices by Using the Programmer 186 Creating Secondary Programming Files 187 Using the Quartus II Software to Program Via a Remote JTAG Server 194 11
CHAPTER 11: PROGRAMMING & CONFIGURATION INTRODUCTION Introduction Once you have successfully compiled a project with the Quartus® II software, you can program or configure an Altera® device. The Assembler module of the Quartus II Compiler generates programming files that the Quartus II Programmer can use to program or configure a device with Altera programming hardware. You can also use a stand-alone version of the Quartus II Programmer to program and configure devices.
CHAPTER 11: PROGRAMMING & CONFIGURATION INTRODUCTION ! Using the quartus_asm executable You can also run the Assembler separately at the command prompt or in a script by using the quartus_asm executable. You must run the Quartus II Fitter executable, quartus_fit, successfully before running the Assembler. The quartus_asm executable creates a separate text-based report file that can be viewed with any text editor.
CHAPTER 11: PROGRAMMING & CONFIGURATION INTRODUCTION The Programmer uses the POFs and SOFs generated by the Assembler to program or configure all Altera devices supported by the Quartus II software. You use the Programmer with Altera programming hardware, such as the MasterBlaster™, ByteBlasterMV™, ByteBlaster™ II, USB-Blaster™, or EthernetBlaster download cable; or the Altera Programming Unit (APU).
CHAPTER 11: PROGRAMMING & CONFIGURATION INTRODUCTION ! Using the quartus_pgm executable You can also run the Programmer separately at the command prompt or in a script by using the quartus_pgm executable. You may need to run the Assembler executable, quartus_asm, in order to produce a programming file before running the Programmer.
CHAPTER 11: PROGRAMMING & CONFIGURATION PROGRAMMING ONE OR MORE DEVICES BY USING THE PROGRAMMER f For Information About Refer To Altera programming hardware Altera Programming Unit User Guide, MasterBlaster Serial/USB Communications Cable User Guide, ByteBlaster II Download Cable User Guide, ByteBlasterMV Download Cable User Guide, USB-Blaster Download Cable User Guide, and EthernetBlaster Download Cable User Guide on the Altera web site Programming hardware installation Quartus II Installation & Lic
CHAPTER 11: PROGRAMMING & CONFIGURATION CREATING SECONDARY PROGRAMMING FILES 5. Select an appropriate programming mode, such as Passive Serial mode, JTAG mode, Active Serial Programming mode, or In-Socket Programming mode. 6. Depending on the programming mode, you can add, delete, or change the order of programming files and devices in the CDF. You can direct the Programmer to detect Altera-supported devices in a JTAG Chain automatically and add them to the device list of the CDF.
CHAPTER 11: PROGRAMMING & CONFIGURATION CREATING SECONDARY PROGRAMMING FILES Creating Other Programming File Formats You can use the Create/Update > Create JAM, SVF, or ISC File command (File menu) to create Jam Files, Jam Byte-Code Files, Serial Vector Format Files, or In System Configuration Files. These files can then be used in conjunction with Altera programming hardware or an intelligent host to configure any Altera device supported by the Quartus II software.
CHAPTER 11: PROGRAMMING & CONFIGURATION CREATING SECONDARY PROGRAMMING FILES Figure 4. ISP CLAMP State Editor Dialog Box The following steps describe the basic flow for creating Jam Files, Jam ByteCode Files, Serial Vector Format Files, In System Configuration Files, or I/O Pin State Files: 1. Perform a full compilation of the design, or at least run the Analysis & Synthesis, Fitter, and Assembler modules of the Compiler. The Assembler automatically creates SOFs and POFs for the design. 2.
CHAPTER 11: PROGRAMMING & CONFIGURATION CREATING SECONDARY PROGRAMMING FILES 6. If you want to create I/O Pin State Files, choose Create/Update > Create/Update IPS File (File menu), and in the ISP CLAMP State Editor dialog box (File menu), specify the appropriate ISP CLAMP state pin settings and specify a name for the file.
CHAPTER 11: PROGRAMMING & CONFIGURATION CREATING SECONDARY PROGRAMMING FILES Figure 5. Convert Programming Files Dialog Box For a POF for an EPC4, EPC8, or EPC16 configuration device, you can also specify the following information: ■ ■ ■ ■ ■ ■ Establish different configuration bitstreams, which are stored in pages in the configuration memory space. Create parallel chains of SOFs within each page. Arrange the order of SOFs and Hexadecimal (Intel-Format) Files (.hex) stored in flash memory.
CHAPTER 11: PROGRAMMING & CONFIGURATION CREATING SECONDARY PROGRAMMING FILES ■ ■ Add or remove SOF Data items. If you wish, create Memory Map Files, and generate remote update difference files and local update difference files. You can also use the Convert Programming Files dialog box to arrange and combine multiple SOFs into a single POFs in Active Serial Configuration mode.
CHAPTER 11: PROGRAMMING & CONFIGURATION CREATING SECONDARY PROGRAMMING FILES 7. (Optional) Add, remove, or change the order of SOFs and POFs to be converted for one or more SOF Data item(s) or POF Data item. 8. (Optional) Add a HEX File to a Bottom Boot Data or Main Block Data item for a POF for an EPC4, EPC8, or EPC16 configuration device, and specify additional properties of SOF Data items, POF Data items, and HEX Files. 9.
CHAPTER 11: PROGRAMMING & CONFIGURATION USING THE QUARTUS II SOFTWARE TO PROGRAM VIA A REMOTE JTAG SERVER Using the Quartus II Software to Program Via a Remote JTAG Server In the Hardware Setup dialog box, which is available from the Hardware button in the Programmer window or from the Edit menu, you can add remote JTAG servers, which you can connect to, for example, to use programming hardware that is not available on your computer, and configure local JTAG server settings so remote users can connect to y
Chapter Twelve Debugging What’s in Chapter 12: Introduction 196 Using the SignalTap II Logic Analyzer 197 Using SignalProbe 205 Using the In-System Memory Content Editor 208 Using the RTL Viewer & Technology Map Viewer 210 Using the Chip Editor 211 12
CHAPTER 12: DEBUGGING INTRODUCTION Introduction The Quartus® II SignalTap® II Logic Analyzer and the SignalProbe™ feature analyze internal device nodes and I/O pins while operating in-system and at system speeds. The SignalTap II Logic Analyzer uses an embedded logic analyzer to route the signal data through the JTAG port to either the SignalTap II Logic Analyzer or an external logic analyzer or oscilloscope, based on user-defined trigger conditions.
CHAPTER 12: DEBUGGING USING THE SIGNALTAP II LOGIC ANALYZER Figure 2.
CHAPTER 12: DEBUGGING USING THE SIGNALTAP II LOGIC ANALYZER Setting Up & Running the SignalTap II Logic Analyzer To use the SignalTap II Logic Analyzer, you must first create a SignalTap II File (.stp), which includes all the configuration settings and displays the captured signals as a waveform. Once you have set up the SignalTap II File, you can compile the project, program the device, and the use the logic analyzer to acquire and analyze data.
CHAPTER 12: DEBUGGING USING THE SIGNALTAP II LOGIC ANALYZER 5. If necessary, specify Advanced Trigger conditions. 6. Compile the design. 7. Program the device. 8. Acquire and analyze signal data in the Quartus II software or using an external logic analyzer or oscilloscope. Figure 3 shows the SignalTap II Logic Analyzer. Figure 3.
CHAPTER 12: DEBUGGING USING THE SIGNALTAP II LOGIC ANALYZER ! Using the Stand-Alone SignalTap II Logic Analyzer If you want to use only the SignalTap II Logic Analyzer, you can use the stand-alone graphical user interface version of the SignalTap II Logic Analyzer, quartus_stpw.
CHAPTER 12: DEBUGGING USING THE SIGNALTAP II LOGIC ANALYZER Figure 4. Advanced Triggers Tab of the SignalTap II Window You can configure the logic analyzer with up to ten trigger levels, helping you to view only the most significant data. You can specify four separate trigger positions: pre, center, post, and continuous. The trigger position allows you to specify the amount of data that should be acquired before the trigger and the amount that should be acquired after the trigger in the selected instance.
CHAPTER 12: DEBUGGING USING THE SIGNALTAP II LOGIC ANALYZER incremental routing is used, in the SignalTap II Logic Analyzer page of the Settings dialog box (Assignments menu). Also, you must reserve trigger or data nodes for SignalTap II incremental routing using the Trigger Nodes allocated and Data Nodes allocated boxes before compiling the design. You can find nodes for SignalTap II incremental routing sources by selecting SignalTap II: post-fitting in the Filter list in the Node Finder.
CHAPTER 12: DEBUGGING USING THE SIGNALTAP II LOGIC ANALYZER 3. Create and open a SignalTap II File. 4. Turn on the Incremental Compile option in the SignalTap II Logic Analyzer Instance Manager next to the instance you want to compile incrementally (see Figure 3 on page 199).
CHAPTER 12: DEBUGGING USING THE SIGNALTAP II LOGIC ANALYZER Figure 5. SignalTap II Waveform View The Waveform Export utility allows you to export the acquired data to the following industry-standard formats that can be used by EDA tools: ■ ■ ■ ■ ■ ■ Comma Separated Values File (.csv) Table File (.tbl) Value Change Dump File (.vcd) Vector Waveform File (.vwf) Joint Photographic Experts Group File (.jpeg) Bitmap File (.
CHAPTER 12: DEBUGGING USING SIGNALPROBE Figure 6. Mnemonic Table Setup Dialog Box f For Information About Refer To Using the SignalTap II Logic Analyzer “Design Debugging Using SignalTap II Embedded Logic Analyzer,” in the Quartus II Handbook, vol.
CHAPTER 12: DEBUGGING USING SIGNALPROBE The SignalProbe feature allows you to specify which signals in the design to debug, perform a SignalProbe compilation that connects those signals to unused or reserved output pins, and then send the signals to an external logic analyzer. You can use the Node Finder when assigning pins to find the available SignalProbe sources. A SignalProbe compilation typically takes approximately 20% to 30% of the time required for a normal compilation.
CHAPTER 12: DEBUGGING USING SIGNALPROBE Figure 7. Assign SignalProbe Pins Dialog Box When reserving SignalProbe pins, you can also use the register pipelining feature to ignore jitter, to force signal states to output on a clock edge, or to delay a signal output. You can also use register pipelining to synchronize multiple SignalProbe outputs from a bus of signals, or to prevent SignalProbe routing from becoming the critical path because of fMAX changes.
CHAPTER 12: DEBUGGING USING THE IN-SYSTEM MEMORY CONTENT EDITOR f For Information About Refer To Using the SignalProbe feature “Quick Design Debugging Using SignalProbe,” in the Quartus II Handbook, vol. 3, on the Altera web site “SignalProbe Introduction” in Quartus II Help Using TCL commands with the SignalProbe feature “Tcl Scripting” in the Quartus II Handbook, vol.
CHAPTER 12: DEBUGGING USING THE IN-SYSTEM MEMORY CONTENT EDITOR ■ HEX Editor: used to make edits and save changes to in-system memory at run-time, to display the current data within the memory block, and to update or offload selected sections of a memory block. You can use the Go To command (right button pop-up menu) to automatically go to a specific data address within a specific memory block within a specific instance. Words are displayed with each hexadecimal value separated by a space.
CHAPTER 12: DEBUGGING USING THE RTL VIEWER & TECHNOLOGY MAP VIEWER f For Information About Refer To Using the In-System Memory Content Editor “In-System Editing of Memory and Constants,” in the Quartus II Handbook, vol. 3, on the Altera web site “Overview: Using the In-System Memory Content Editor” in Quartus II Help Using the RTL Viewer & Technology Map Viewer You can use the RTL Viewer to analyze your design after analysis and elaboration has been performed.
CHAPTER 12: DEBUGGING USING THE CHIP EDITOR Using the Chip Editor You can use the Chip Editor in conjunction with the SignalTap II and SignalProbe debugging tools to speed up design verification and incrementally fix bugs uncovered during design verification. After you run the SignalTap II Logic Analyzer or verify signals with the SignalProbe feature, you can use the Chip Editor to view details of post-compilation placement and routing.
Chapter Thirteen Engineering Change Management What’s in Chapter 13: Introduction 214 Identifying Delays & Critical Paths by Using the Chip Editor 215 Editing Atoms in the Chip Editor 217 Modifying Resource Properties by Using the Resource Property Editor 217 Viewing & Managing Changes with the Change Manager 219 Verifying the Effect of ECO Changes 221 13
CHAPTER 13: ENGINEERING CHANGE MANAGEMENT INTRODUCTION Introduction The Quartus® II software allows you to make small modifications, often referred to as engineering change orders (ECO), to a design after a full compilation. These ECO changes can be made directly to the design database, rather than to the source code or the Quartus II Settings and Configuration File (.qsf). Making the ECO change to the design database allows you to avoid running a full compilation in order to implement the change.
CHAPTER 13: ENGINEERING CHANGE MANAGEMENT IDENTIFYING DELAYS & CRITICAL PATHS BY USING THE CHIP EDITOR 7. Use the Check and Save All Netlist Changes command (Edit menu) to check the legality of the change for all of the other resources in the netlist. 8. Run the Assembler to generate a new programming file or run the EDA Netlist Writer again to generate a new netlist. If you want to verify timing changes, you can run the Timing Analyzer.
CHAPTER 13: ENGINEERING CHANGE MANAGEMENT IDENTIFYING DELAYS & CRITICAL PATHS BY USING THE CHIP EDITOR The Chip Editor displays all the resources of the device, such as interconnects and routing lines, logic array blocks (LABs), RAM blocks, DSP blocks, I/Os, rows, columns, and the interfaces between blocks and interconnects and other routing lines.
CHAPTER 13: ENGINEERING CHANGE MANAGEMENT EDITING ATOMS IN THE CHIP EDITOR Editing Atoms in the Chip Editor The Chip Editor also allows you to create new atoms or move existing atoms to other locations. You can also remove atoms. These changes are reflected in the Change Manager. You can create a new atom by selecting resource location in the Chip Editor window, choosing Create Atom (right button pop-up menu), and specifying a new name for the atom.
CHAPTER 13: ENGINEERING CHANGE MANAGEMENT MODIFYING RESOURCE PROPERTIES BY USING THE RESOURCE PROPERTY EDITOR Figure 3.
CHAPTER 13: ENGINEERING CHANGE MANAGEMENT VIEWING & MANAGING CHANGES WITH THE CHANGE MANAGER resource. You can also view a summary of your changes in the Change Manager. Refer to the next section, “Viewing & Managing Changes with the Change Manager,” for more information. f For Information About Refer To Engineering change management and using the Resource Property Editor “Engineering Change Management” in the Quartus II Handbook, vol.
CHAPTER 13: ENGINEERING CHANGE MANAGEMENT VIEWING & MANAGING CHANGES WITH THE CHANGE MANAGER The log view of the Change Manager displays the following information for each ECO change: ■ ■ ■ ■ ■ ■ ■ ■ Index Node Name Change Type Old Value Target Value Current Value Disk Value Comments (your comments about the ECO change) Green shading in the Current Value column indicates that the changes have been applied to the current value.
CHAPTER 13: ENGINEERING CHANGE MANAGEMENT VERIFYING THE EFFECT OF ECO CHANGES f For Information About Refer To Engineering change management and using the Change Manager “Engineering Change Management” in the Quartus II Handbook, vol. 1, on the Altera web site “Design Analysis and Engineering Change Management with the Chip Editor,” in the Quartus II Handbook, vol.
Chapter Fourteen Formal Verification What’s in Chapter 14: Introduction 224 Using EDA Formal Verification Tools 225 Specifying Additional Settings 227 14
CHAPTER 14: FORMAL VERIFICATION INTRODUCTION Introduction The Quartus II software allows you to use formal verification EDA tools to verify the logical equivalence between source design files and Quartus II output files. Figure 1 shows the formal verification flow. Figure 1. Formal Verification Flow RTL Verilog HDL or VHDL source design files (.v, .vhd) EDA Synthesis Tools Verilog Quartus Mapping Files (.
CHAPTER 14: FORMAL VERIFICATION USING EDA FORMAL VERIFICATION TOOLS an EDA synthesis tool and the Verilog Output Files (.vo) generated by the Quartus II software. For the Cadence Encounter Conformal software, the Quartus II software also allows you to verify the logical equivalence between RTL VHDL design files (.vhd) or Verilog HDL design files (.v) and Quartus II–generated Verilog Output Files. Figure 2 shows which file types are compared in formal verification. Figure 2.
CHAPTER 14: FORMAL VERIFICATION USING EDA FORMAL VERIFICATION TOOLS Table 1. Quartus II–Supported EDA Formal Verification Tools Verilog Quartus Mapping File (.vqm) Support RTL Verilog HDL or VHDL Design File Support Cadence Encounter Conformal v v Synopsys Formality v Formal Verification Tool Name In the Formal Verification page under EDA Tool Settings in the Settings dialog box (Assignments menu), you can specify the EDA formal verification tool you will use. See Figure 3. Figure 3.
CHAPTER 14: FORMAL VERIFICATION SPECIFYING ADDITIONAL SETTINGS f For Information About Refer To Using Cadence Encounter Conformal software “Cadence Encounter Conformal Support” in the Quartus II Handbook, vol. 3, on the Altera web site “Overview: Using the Encounter Conformal Software with the Quartus II Software” in Quartus II Help Using Synopsis Formality software “Synopsis Formality Support” in the Quartus II Handbook, vol.
CHAPTER 14: FORMAL VERIFICATION SPECIFYING ADDITIONAL SETTINGS f 228 ■ For Information About Refer To Additional guidelines and options for using Synopsis Formality software “Synopsis Formality Support” in the Quartus II Handbook, vol.
Chapter Fifteen System-Level Design What’s in Chapter 15: Introduction 230 Creating SOPC Designs with SOPC Builder 232 Creating DSP Designs with the DSP Builder 234 15
CHAPTER 15: SYSTEM-LEVEL DESIGN INTRODUCTION Introduction The Quartus® II software supports the SOPC Builder and DSP Builder system-level design flows. System-level design flows allow engineers to rapidly design and evaluate system-on-a-programmable-chip (SOPC) architectures and design at a higher level of abstraction. The SOPC Builder is an automated system development tool that dramatically simplifies the task of creating high-performance SOPC designs.
CHAPTER 15: SYSTEM-LEVEL DESIGN INTRODUCTION Figure 2. DSP Builder Design Flow DSP Builder MATLAB/ Simulink Intellectual property (IP) SignalCompiler Verilog design files, VHDL design files (.v, .vhd) & Tcl Script Files (.
CHAPTER 15: SYSTEM-LEVEL DESIGN CREATING SOPC DESIGNS WITH SOPC BUILDER Creating SOPC Designs with SOPC Builder The SOPC Builder, which is included with the Quartus II software, provides a standardized, graphical environment for creating SOPC designs composed of components such as CPUs, memory interfaces, standard peripherals, and user-defined peripherals. The SOPC Builder allows you to select and customize the individual components and interfaces of your system module.
CHAPTER 15: SYSTEM-LEVEL DESIGN CREATING SOPC DESIGNS WITH SOPC BUILDER SOPC Builder can import or provide an interface to user-defined blocks of logic. There are four mechanisms for using an SOPC Builder system with user-defined logic: simple PIO connection, instantiation inside the system module, bus interface to external logic, and publishing a local SOPC Builder component.
CHAPTER 15: SYSTEM-LEVEL DESIGN CREATING DSP DESIGNS WITH THE DSP BUILDER SOPC Builder can also create software development kit (SDK) software components, such as header files, generic peripheral drivers, custom software libraries, and OS/real-time operating system (RTOS kernels), to provide a complete design environment when the system is generated.
CHAPTER 15: SYSTEM-LEVEL DESIGN CREATING DSP DESIGNS WITH THE DSP BUILDER software design with a physical FPGA board implementing a portion of that design. You define the contents and function of the FPGA by creating and compiling a Quartus II project. A simple JTAG interface between Simulink and the FPGA board links the two.
CHAPTER 15: SYSTEM-LEVEL DESIGN CREATING DSP DESIGNS WITH THE DSP BUILDER You can use the automated flow to control the entire synthesis and compilation flow from within the MATLAB/Simulink design environment. The SignalCompiler block creates VHDL Design Files and Tcl scripts, performs synthesis in the Quartus II, LeonardoSpectrum, or Synplify software, compiles the design in the Quartus II software, and can also optionally download the design to a DSP development board.
Chapter Sixteen Software Development What’s in Chapter 16: Introduction 238 Using the Software Builder in the Quartus II Software 238 Specifying Software Build Settings 239 Generating Software Output Files 239 16
CHAPTER 16: SOFTWARE DEVELOPMENT INTRODUCTION Introduction The Quartus® II Software Builder is an integrated programming tool that transforms software source files into a flash programming file or passive programming files for configuring an Excalibur™ device, or files that contain memory initialization data for the embedded processor stripe of an Excalibur device.
CHAPTER 16: SOFTWARE DEVELOPMENT SPECIFYING SOFTWARE BUILD SETTINGS ! Using the quartus_swb executable You can also run the Software Builder separately at the command prompt or in a script by using the quartus_swb executable.
CHAPTER 16: SOFTWARE DEVELOPMENT GENERATING SOFTWARE OUTPUT FILES Quartus II software) and the stand-alone MegaWizard® Plug-In Manager to generate passive programming files and flash programming files outside the Quartus II software. For more information on using the makeprogfile utility, type makeprogfile -h r at a command prompt.
CHAPTER 16: SOFTWARE DEVELOPMENT GENERATING SOFTWARE OUTPUT FILES 2. Run the ARM-based Excalibur MegaWizard Plug-In to generate a System Build Descriptor File (.sbd). 3. If you want the flash programming file to contain configuration data for the programmable logic device (PLD) portion of the Excalibur device, compile the design to generate a Slave Binary Image File (.sbi). 4. Specify the toolset directory and software build settings.
CHAPTER 16: SOFTWARE DEVELOPMENT GENERATING SOFTWARE OUTPUT FILES 3. A linker links the boot data file with a binary bootloader file to create an Executable and Linkable Format File (.elf). 4. A code converter converts the Executable and Linkable Format File into a flash programming file with the name _flash.hex.
CHAPTER 16: SOFTWARE DEVELOPMENT GENERATING SOFTWARE OUTPUT FILES 4. Specify the software toolset directory and software build settings. To generate a flash programming file, you must specify the output file type and file name, turn on Passive configuration, and specify the PSOF in the Software Build Settings page of the Settings dialog box (Assignments menu). 5. Start the Software Builder. Figure 2 shows the flow for using the Software Builder to create passive programming files. Figure 2.
CHAPTER 16: SOFTWARE DEVELOPMENT GENERATING SOFTWARE OUTPUT FILES Generating Memory Initialization Data Files Binary Files (.bin), HEX Files, and Library Files (.a) contain the memory initialization data for the Excalibur embedded processor stripe. The following steps describe the basic flow for creating BIN Files, HEX Files, and Library Files with the Software Builder: 1. Create the software source files and add them to the project. 2. Specify the software toolset directory and software build settings.
CHAPTER 16: SOFTWARE DEVELOPMENT GENERATING SOFTWARE OUTPUT FILES f 2. If you are generating BIN Files or HEX Files, the linker links the object files and generates an intermediate ELF File, and the code converter converts the ELF File into a BIN File or HEX File. 3. If you are generating a Library File, the Software Builder uses the Software Builder Archiver to process the object files into a Library File.
Chapter Seventeen Installation, Licensing & Technical Support What’s in Chapter 17: Installing the Quartus II Software 248 Licensing the Quartus II Software 249 Getting Technical Support 251 17
CHAPTER 17: INSTALLATION, LICENSING & TECHNICAL SUPPORT INSTALLING THE QUARTUS II SOFTWARE Installing the Quartus II Software You can install the Quartus® II software on the following platforms: ■ Pentium PC operating at 400 MHz or faster, running one of the following Windows operating systems: – – – ■ Pentium III or Pentium 4 PC operating at 400 MHz or faster, running one of the following Linux operating systems: – – – f Microsoft Windows NT version 4.
CHAPTER 17: INSTALLATION, LICENSING & TECHNICAL SUPPORT LICENSING THE QUARTUS II SOFTWARE Licensing the Quartus II Software To use Altera®-provided software, you need to obtain and set up an Altera subscription license. An Altera subscription enables the following software: ■ ■ Altera Quartus II software Mentor Graphics® ModelSim®-Altera software Altera offers several types of software subscriptions. Table 1 shows the different license and subscription options that are available. Table 1.
CHAPTER 17: INSTALLATION, LICENSING & TECHNICAL SUPPORT LICENSING THE QUARTUS II SOFTWARE 250 ■ – Enable 30-day evaluation period with no license file (no programming file support). This option allows you to evaluate the Quartus II software, without programming file support, for 30 days. After the 30-day grace period is over, you must obtain a valid license file from the Licensing section of the Altera web site at www.altera.com/licensing, and then follow the remaining steps in this procedure.
CHAPTER 17: INSTALLATION, LICENSING & TECHNICAL SUPPORT GETTING TECHNICAL SUPPORT f For Information About Refer To Detailed information about licensing the Quartus II software, modifying the license file, and specifying the license file location Quartus II Installation & Licensing for PCs manual on the Altera web site General information about Quartus II licensing “Overview: Obtaining a License File” and “Specifying a License File” in Quartus II Help Altera software licensing Application Note 340 (
CHAPTER 17: INSTALLATION, LICENSING & TECHNICAL SUPPORT GETTING TECHNICAL SUPPORT If you are not a current Altera subscription user, you can still register for an Altera.com account. For information about other technical support resources, refer to Table 2. Table 2. Quartus II Technical Support Resources Resource Description Altera web site www.altera.com The Altera web site provides information on Altera and all of its products. Support Center www.altera.
Chapter Eighteen Documentation & Other Resources What’s in Chapter 18: Getting Online Help 254 Using the Quartus II Online Tutorial 255 Other Quartus II Software Documentation 256 Other Altera Literature 257 18
CHAPTER 18: DOCUMENTATION & OTHER RESOURCES GETTING ONLINE HELP Getting Online Help The Quartus® II software includes a platform-independent Help system that provides comprehensive documentation for the Quartus II software and more details about the specific messages generated by the Quartus II software. You can view Help in one of the following ways: To search through a list of Help topics by keyword Choose Index (Help menu) to perform a search by using the Index tab.
CHAPTER 18: DOCUMENTATION & OTHER RESOURCES USING THE QUARTUS II ONLINE TUTORIAL f For Information About Refer To Using Quartus II Help “Using Quartus II Help Effectively” and “Help Menu Commands” in Quartus II Help “Using Quartus II Help” in the Quartus II Installation & Licensing for PCs manual and Quartus II Installation & Licensing for UNIX and Linux Workstations manual Using the Quartus II Online Tutorial The online tutorial introduces you to the features of the Quartus II design software.
CHAPTER 18: DOCUMENTATION & OTHER RESOURCES OTHER QUARTUS II SOFTWARE DOCUMENTATION ! More Information About Using the Quartus II Tutorial You must have installed support for Cyclone™ EP1C6 devices if you want to complete the Basic or LogicLock tutorial. In addition, you must have installed support for the MAX® EPM570 and Stratix EP1S25 devices if you want to complete the Optional MAX+PLUS II Conversion and Stratix tutorial modules. The tutorial is designed for display online.
CHAPTER 18: DOCUMENTATION & OTHER RESOURCES OTHER ALTERA LITERATURE Table 1. Additional Quartus II Documentation (Part 2 of 2) Document Description Where to Find It Quartus II Scripting Reference Manual Provides information about command-line and Tcl commands and scripting.
CHAPTER 18: DOCUMENTATION & OTHER RESOURCES OTHER ALTERA LITERATURE literature in order to provide more information on the latest features of Altera tools and devices, and to provide additional information that Altera customers have requested. ! Searching through Altera Literature with Altera Find Answers You can use Altera Find Answers, which is available from the Support Center section of the Altera web site at www.altera.
Index A B ADS Standard Tools software toolset 238 AHDL 46 AHDL Include Files (.inc) 44 Altera Find Answers 252 Altera Hardware Description Language (AHDL) 46 Altera Megafunction Partners Program (AMPP) 48 Altera on the Web command 251 Altera Programming Unit (APU) 184 Altera web site 252 Altera.
INDEX Convert Programming Files command 183, 187 Copy Project command 35 Create command 218 Create/Update > Create Jam, SVF, or ISC File command 183, 187 Create/Update > Create/Update IPS File command 183, 187, 188 Create/Update command 45, 46 critical paths 164 Customize dialog box 6, 7 customizing look and feel 6 D debugging see SignalTap II Logic Analyzer; SignalProbe feature Design Assistant 4, 79, 98 Design Assistant page 79 design constraints 56 design entry 34 design partitions 62, 119 Design Parti
INDEX Floorplan Editor see Timing Closure floorplan flows for compilation 5, 21 formal verification design flow 224 performing with EDA tools 225 specifying settings 227 full compilation 4 functional simulation EDA tools 132 Quartus II Simulator 136 G GNUPro for ARM software toolset 238 Graphic Design Files (.gdf) 43, 44 Graphic Editor see Block Editor graphical user interface 3 H Help, getting 254 Hexadecimal (Intel-Format) Files (.hex) 191, 240 Hexadecimal (Intel-Format) Output Files (.
INDEX look and feel, customizing 6 LPM 47 M makefile support 27 makeprogfile utility 239 MasterBlaster download cable 184, 197 MATLAB/Simulink environment 235 MAX+PLUS II Assignment & Configuration Files (.acf) 65 MAX+PLUS II look and feel 6 MAX+PLUS II quick menu 7 MAX+PLUS II Simulator Channel Files (.scf) 139 MAX+PLUS II Symbol Files (.
INDEX Programmer 182 quartus_pgm executable 185 quartus_pgmw executable 18 stand-alone version 18, 184 Programmer Object Files (.pof) 182, 186, 187, 242 programming 182 design flow 182 programming hardware 184 programming files converting 183, 187 creating secondary 187 Programming Files tab 187 Project Navigator window 36 Q qmegawiz executable 18 QSF 35, 117, 146 Quartus II Default Settings Files (.qdf) 35 Quartus II look and feel 6 Quartus II Project Files (.
INDEX settings (continued) SignalProbe 206 SignalTap II Logic Analyzer 198, 202 Simulator 60, 138 Software Builder 60, 239, 241, 243, 244 synthesis optimization 78, 167 Timing Analyzer 60 Verilog HDL input 69 VHDL input 69 Settings dialog box 60, 99, 143 shell, Tcl scripting 19 Shop Altera web site 257 Signal Activity Files (.saf) 128, 132, 174 SignalProbe feature 196, 205 compilation 206 design flow 196 reserving pins 207 using 206 SignalProbe Settings page 206 SignalTap II Files (.
INDEX synthesis (continued) Integrated Synthesis 69 netlist optimization 75, 78, 167 performing with EDA tools 72 VHDL and Verilog HDL support 69 Synthesis Netlist Optimizations page 78, 167 System Build Descriptor Files (.
