Embedded System Tools Guide Embedded Development Kit EDK 6.2i UG111 (v1.
R "Xilinx" and the Xilinx logo shown above are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are reserved. CoolRunner, RocketChips, Rocket IP, Spartan, StateBENCH, StateCAD, Virtex, XACT, XC2064, XC3090, XC4005, and XC5210 are registered trademarks of Xilinx, Inc. The shadow X shown above is a trademark of Xilinx, Inc. ACE Controller, ACE Flash, A.K.A.
Embedded System Tools Guide UG111 (v1.4) January 30, 2004 The following table shows the revision history for this document.. Version Revision 06/24/02 1.0 Initial Xilinx EDK (Embedded Processor Development Kit) release. 08/13/02 1.1 EDK (v3.1) release. 09/02/03 1.3 EDK 6.1 release. 01/30/04 1.4 EDK 6.2i release UG111 (v1.4) January 30, 2004 www.xilinx.
Embedded System Tools Guide www.xilinx.com 1-800-255-7778 UG111 (v1.
R Preface About This Guide Welcome to the Embedded Developement Kit. This kit is designed to provide designers with a rich set of design tools and a wide selection of standard peripherals required to build embedded processor systems using MicroBlaze, the industry’s fastest soft processor solution, and the new and unique feature in Virtex-II Pro, the IBM ® PowerPC ® CPU. This guide provides information about the Embedded System Tools (EST) included in the Embedded Development Kit (EDK).
R Preface: About This Guide x Chapter 22, “Address Management” x Chapter 23, “Interrupt Management” Additional Resources For additional information, go to http://support.xilinx.com. The following table lists some of the resources you can access from this website. You can also directly access these resources using the provided URLs. Resource EDK Home Description/URL Embedded Development Kit home page, FAQ and tips. http://www.xilinx.com/edk EDK Examples A set of complete EDK examples. http://www.
R Conventions Typographical The following typographical conventions are used in this document: Convention Meaning or Use Example Courier font Messages, prompts, and program files that the system displays speed grade: - 100 Courier bold Literal commands that you enter in a syntactical statement ngdbuild design_name Commands that you select from a menu File o Open Keyboard shortcuts Ctrl+C Variables in a syntax statement for which you must supply values ngdbuild design_name References to oth
R Preface: About This Guide Online Document The following conventions are used in this document: Convention 8 Meaning or Use Example See the section “Additional Resources” for details. Blue text Cross-reference link to a location in the current document Red text Cross-reference link to a location in another document See Figure 2-5 in the Virtex-II Handbook. Blue, underlined text Hyperlink to a website (URL) Go to http://www.xilinx.com for the latest speed files. www.xilinx.
Table of Contents Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Typographical . . . . . . . . . . . . . . . . .
R XPS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Editor Workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R XPS “No Window” Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Available Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating A New Empty Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating A New Project With Given MHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Opening An Existing Project .
R Netlist files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Documentation files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Finishing Peripheral Import . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Organization of generated files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Options file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDL Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts and Interrupt Controller . . . . . . . . . . . . . . . . . .
R Verilog Language Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 VHDL Peripheral Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 VHDL Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R PLB Slave Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Entity-level VHDL Attributes for Automation Support . . . . . . . . . . . . . . . . . . . . . . . ADDR_SLICE Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AWIDTH Attribute . . . . . . . . .
R Chapter 9: Format Revision Tool Revup from EDK 6.1 to EDK 6.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Tool Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Revup from EDK 3.2 to EDK 6.1 . . . . . . . . . . . . . . . . . . . . . . . .
R -mxl-stack-check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -mxl-barrel-shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -mxl-gp-opt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -xl-mode-executable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R Example debug session with program running in ISOCM memory and accessing DCR registers 193 Example debug session for special JTAG chain setup (Non-Xilinx devices) . . . . . . 194 PowerPC Simulator Target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Running PowerPC ISS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 PowerPC Simulator target options . . . . . . . . . . . . . . . . . . . . .
R MHS Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Global Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R BUS_STD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUS_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EXCLUDE_BUSIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SHARES_ADDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R RANGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 SYSLEVEL_UPDATE_PROC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Parameter Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R C_PLB_MID_WIDTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 C_PLB_NUM_MASTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 C_PLB_NUM_SLAVES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 Reserved Port Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 Clock and Reset Ports . .
R PSF Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 Parameter INT_HANDLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 Instance Specific Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 OS, Driver, Library and Processor Block Parameters . . . . . . . . . . . . . . . . . . . . . . . . . .
R Library Generation (Generate) Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 Chapter 21: Microprocessor Driver Definition (MDD) Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Driver Definition Files . . . . . . . . . . . . . . . . . . .
R Advanced User Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Different Base Address, Contiguous User Address Space . . . . . . . . . . . . . . . . . . . . . . Different Base Address, Non-contiguous User Address Space . . . . . . . . . . . . . . . . . . . Linker Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Minimal Linker Script . . . . . . . . . . . . . . . . . . . . . .
R Chapter 1 Embedded System Tools Architecture This chapter describes the Embedded System Tools (EST) architecture and flows for the Xilinx embedded processors, PowerPC 405 and MicroBlaze. The chapter contains the following sections. x “Tool Architecture Overview” x “Tool Flows” x “Some Useful Tools” x “Verifying Tools Setup” Tool Architecture Overview Figure 1-1 depicts the embedded software tool architecture.
R Chapter 1: Embedded System Tools Architecture Tool Flows A typical embedded system design project involves the following phases: x hardware platform creation, x hardware platform verification (simulation), x software platform creation, x software application creation, and x software verification (debugging). Xilinx provides tools to assist in all the above design phases.
R Tool Flows Note: After running PlatGen, FPGA implementation tools (ISE) are run to complete the implementation of the hardware. Typically, XPS spawns off the ProjNav front end for the implementation tools, allowing full control over the implementation. See ISE documentation for more info on the ISE tools. At the end of the ISE flow, a bitstream is generated to configure the FPGA. This bitstream includes initialization information for BRAM memories on the FPGA chip.
R Chapter 1: Embedded System Tools Architecture MSS File SW Spec Ed. Emacs, XPS MSS Editor MSS, MHS, lib/*.c, lib/*.h XPS SW Plat. Gen libgen libc.a, libXil.a X9881 Figure 1-4: Software Platform Software Application Creation and Verification The software application is the code that runs on the hardware and software platforms. The source code for the application is written in a high level language such as C or C++, or in assembly language.
R Some Useful Tools Some Useful Tools Xilinx Platform Studio The Xilinx Platform Studio (XPS) tool provides a GUI for creating the MHS and MSS files for the hardware and software flow. XPS also provides source file editor capability and project and process management capability. XPS is used for managing the complete tool flow, that is, both hardware and software implementation flows. Please see Chapter 2, “Xilinx Platform Studio (XPS)” for more information.
R Chapter 1: Embedded System Tools Architecture GNU Compiler Tools XPS calls GNU compiler tools for compiling and linking application executables for each processor in the system. Given a set of C source files, a Microprocessor executable is created as follows. MicroBlaze mb-gcc file1.c file2.c This command compiles and links the files into an executable that can run on the MicroBlaze processor. The output executable is in a.out.
R Some Useful Tools Debugging Using Hardware: software intrusive Create your application executable using the compiler. For example mb-gcc -g -xl-mode-xmdstub file1.c file2.c This command creates the Microprocessor executable a.out, linked with the C runtime library crt1.o and starting at physical address 0x400, and with debugging information that can be read by mb-gdb (or powerpc-eabi-gdb if compilation was done for PowerPC).
R Chapter 1: Embedded System Tools Architecture The xmd server is not needed in this mode. After loading the program in mb-gdb, Click on the “Run” icon and in the mb-gdb Target Selection dialog, choose “Simulator”. Use this mechanism only if your program does not attempt to access any peripherals (not even via a print call). Dumping an Object/Executable File The mb-objdump utility lets you see the contents of an object (.o) or executable (.out) file.
R Chapter 2 Xilinx Platform Studio (XPS) This chapter describes the Xilinx Platform Studio (XPS) IDE for the Xilinx Embedded Processors, MicroBlaze and PowerPC. Xilinx Platform Studio (XPS) provides an integrated environment for creating the software and hardware specification flows for an Embedded Processor system. It also provides an editor and a project management interface to create and edit source code. XPS offers customization of tool flow configuration options.
R Chapter 2: Xilinx Platform Studio (XPS) calling the tools in the correct order using the makefile mechanism. Figure 2-1 provides a detailed view of processes supported by XPS. XMP File MHS File Project Management User Program Sources Program Sources Management MSS Engine Make File Process Management Platgen Libgen Implementation Tools Compiler Data2MEM X10125 Figure 2-1: XPS Process Tools Supported Table 2-1 describes the tools that are supported in the XPS.
R Project Management Table 2-1: Tools supported in XPS Tool Function Reference/Notes XMD Opens an XMD terminal for the user for on-board debug. XMD Documentation Project Navigator Export and Import Export and Import design to Project Navigator for synthesis and implementation of design. Flow is an alternative to the XFlow mechanism in XPS.
R Chapter 2: Xilinx Platform Studio (XPS) x The MHS uses a peripheral which is not present either in the Xilinx EDK installation area or in pcores directory of the XPS project directory. x The MSS uses a driver which is not present either in the Xilinx EDK installation area or in the drivers directory of the XPS project directory. The concept of a Search Path directory, and its subdirectory structure is explained in detail in Platform Generator and Library Generator chapters.
R XPS Interface XPS Interface Figure 2-2: XPS (Xilinx Platform Studio) t Figure 2-2 shows a screenshot of XPS. XPS opens three main windows by default. Editor Workspace The main editor workspace appears on the right in XPS in Figure 2-2. The workspace opens PBD (Platform Block Diagram) file and allows graphical editing of the system. The main workspace also functions as a C source and header file editor of XPS. Users can also view and edit other text files in the main window.
R Chapter 2: Xilinx Platform Studio (XPS) System Tab This tab is one of the four tabs that appear on the left in the XPS window in Figure 2-2. The system tab shows the system in a tree format. There are three sub-trees in this view: x The System BSP tree shows system components (various cores) by their instance names. Each core can have its own sub-tree which displays information corresponding to that instance (for example base address and high address).
R Platform Management Platform Management In order to change the system specification, software settings, and simulation options, XPS supports the following features and processes. Add/Edit Cores (Dialog) A Right click on System BSP item in the System View tab gives a menu option to Add Cores (dialog) to the system. Selecting it brings up a tabbed dialog box that lists all the cores which can be instantiated in the design.
R Chapter 2: Xilinx Platform Studio (XPS) The Libraries table shows all the libraries that are included in the EDK and each library can be included in the design by checking the Use column. The Kernel and OS table can be used to select an OS for the processor system in the design. A standalone OS is selected by default. Please see the Mocroprocessor Software Specification (MSS) for more information. Processor and Driver Parameters This tab shows two tables, Processor Parameters and Driver Parameters.
R Software Application Management Editing Files Double clicking on the source or header file in the Project View window opens the file for editing. The editor supports basic editing functions such as cut, paste, copy and search/replace. The editor highlights basic source code syntax. It also supports file management and printing functions such as saving, printing, and print previews.
R Chapter 2: Xilinx Platform Studio (XPS) Compiler Options A Compiler Option Dialog Window opens up when any active software application name is double-clicked or Set Compiler Option... menu option is chosen for that software application in the Software Projects tree in Applications tab. This dialog has the following four tabs. Environment The tab displays the compiler being used for compiling this application. The compiler used can be changed in the “Software PlatForm Settings” dialog.
R Flow Tool Settings and Required Files Table 2-2 shows the options that are displayed in the compiler options dialog window under various tabs. Table 2-2: Processor Options Option Value Type Description Compiler Options Optimization Level Choose the level of compiler optimization. Equivalent to -O option in gcc. Global Pointer Optimization Compiler Option This option enables global pointer optimization in the compiler. This option is only for MicroBlaze.
R Chapter 2: Xilinx Platform Studio (XPS) Device and Repository The target device for the project can be changed here. There are four different items: Architecture, Device Size, Package, and Speed Grade. Users can specify the Search Path directories here. However, if this option is changed, users must close the project immediately. If this option is changed here, the changes will be effective only if the project is closed and loaded again.This option corresponds to the -lp option of various batch tools.
R Tool Invocation Users can also specify the flow to use for running the Xilinx implementation tools. The available options are XPS (Xflow) and ISE (Project Navigator) flow. Note that if the design is a sub-module, users must use the ISE flow. Please see the “ISE Project Navigator Interface” section described later for details on how to add design components and files to ProjNav project using XPS.
R Chapter 2: Xilinx Platform Studio (XPS) 1. Generate Netlist: This button calls the platform building tool PlatGen with the correct MHS file and produces the netlist files in NGC format. 2. Generate Bitstream: If using XPS for implementation tools, this button calls the tool xflow with the fast_runtime.opt and bitgen.ut files residing in the etc. directory in the project directory. XFlow in turn calls the Xilinx iSE Implementation tools.
R Debug and Simulation Debug and Simulation Users can debug the hardware and the software part of the design either by simulation or by running it on the hardware itself. XPS provides support for invoking the corresponding tools to perform the job. x Xilinx Microprocessor Debug (XMD): Invoke the XMD tool to debug the application software. The XMD-button on the XPS toolbar opens up a XMD shell in the project directory.
R Chapter 2: Xilinx Platform Studio (XPS) Figure 2-3: The PBD Editor PBD Editor Workspace The PBD Editor workspace is the upper right window in the XPS (see Figure 2-4). The workspace contains the block diagram describing the system hardware. Figure 2-4: PBD Editor Workspace 50 www.xilinx.com 1-800-255-7778 Embedded System Tools Guide (EDK 6.2i) UG111 (v1.
R PBD Editor System Tabs The system tabs are in the upper left of the XPS window (see Figure 2-5). Two of the tabs in the window are used in the PBD Editor operation. x The Options tab changes according to the tool that you are using and allows you to set options related to the tool, such as how the Add Bus Connection tool should operate. x The Components tab allows you to select a component (a CPU, Bus Infrastructure component, or peripheral) to instantiate into your system.
R Chapter 2: Xilinx Platform Studio (XPS) 1. Select the project_name.pbd tab in the workspace to display the system block diagram. 2. Select Add o Component or click the Add Component toolbar button. 3. In the Components tab, use the Categories and Components lists to specify the component you are adding. The component you select is attached to the mouse cursor. Note: To make the component selection easier, type the first letter or letters of the component in the Component Name Filter field.
R PBD Editor b. Clicking Add. c. Change the parameter Value in the Explicit Parameter Values table. d. Click Apply. The value entered in the Explicit Parameter Values table overrides the value displayed in the Default Parameter Values table. Setting Symbol Properties Symbol properties determine the appearance of an instance’s block in the workspace. You can modify the size of the symbol drawing or the location of the bus pins on the symbol.
R Chapter 2: Xilinx Platform Studio (XPS) If the type of bus is compatible with the type of pin, connection lines are drawn to show the bus connection. Connecting Ports You can create nets to connect ports on component instances. To create a net, you assign the same net name to all of the ports you want to connect. Port connections cannot be seen as nets drawn on the block diagram. All of the nets shown on the block diagram are bus connections.
R PBD Editor 4. i If you click the heading of a column, the entries in the column are displayed in alphabetical order. If the click the column heading again, the entries in the column are displayed in reverse alphabetical order. i You can remove a system port by selecting it and clicking Remove. When you have finished your edits, click OK. Viewing and Editing All of the Ports in the System You can view and edit the all of the ports in the system (internal and external) in a single dialog box.
R Chapter 2: Xilinx Platform Studio (XPS) 3. In the Component Interrupts dialog box, select the Interrupt you wish to configure in the Interrupt Port box. 4. In the Possible Interrupt Nets box, select the nets that will drive the internet. To select multiple nets, click the first net name, then press the Ctrl key and click the additional net names. Note: If the interrupt port is a scalar port (that is, its range is blank) then only one net may be selected to drive the interrupt.
R PBD Editor Viewing Object Information To view information about an object in the workspace, place the cursor over the object. A box appears supplying information about the object (name, IP name, bus pin type, etc.). Zooming in the Workspace You can use menu commands to zoom the display in the workspace. Zooming Behavior Menu Command Zoom in Select View o Zoom o In, or click the Zoom In toolbar button. Zoom out Select View o Zoom o Out, or click the Zoom Out toolbar button.
R Chapter 2: Xilinx Platform Studio (XPS) Object Toolbar Icon Arc Circle Line Rectangle Text 2. If any options appear in the Options tab, select the appropriate options for the object. 3. Click to start drawing the object. 4. Drag the cursor until the object is the appropriate size. 5. If necessary, move the cursor to adjust the object. For example, when you draw an arc you must move the cursor until the arc appears as you want it to display.
R XPS “No Window” Mode Available Commands XPS-Batch provides you a Tcl shell interface. You can use the commands in Table 2-3. Table 2-3: XPS-Batch commands Command Description load [mhs|xmp|new|mss|] Loads the MHS/XMP file and opens/creates XPS project. Updates project with MSS file. Input is optional when loading MSS. Users can create an empty project with suboption new save Saves the corresponding file.
R Chapter 2: Xilinx Platform Studio (XPS) Creating A New Project With Given MHS For creating a new project, use the command load mhs .mhs. XPS will read in the MHS file and create the new project. The project name will be same as MHS basename. All the files generated will have the same name as MHS. After reading in the MHS file, XPS will also assign various default drivers to each of the peripheral instance, if a driver is known and available to XPS.
R XPS “No Window” Mode Table 2-4: Options for command xset and xget package Set package of the target device speedgrade Set speedgrade of the target device searchpath [dirs] Set the Search Path as semicolon separated list of directories hier [top|sub] Set the design hierarchy topinst [instname] Set the name by which processor design is instantiated (if submodule) hdl [vhdl|verilog] Set HDL language to be used sim_model [structural|behavioral Set current simulation mode |timing] simulator [
R Chapter 2: Xilinx Platform Studio (XPS) Table 2-5: Options for command run libs Generate software libraries bsp Generate VxWorks bsp for given ppc405 system program Compile user program into ELF file(s) init_bram Update bitstream with BRAM initialization information ace Generate SystemACE file after .
R XPS “No Window” Mode Adding a Program File to a Software Application Users can add any program file (C source or header files) to an existing software application using the xadd_swapp_progfile command. The name of the swapp to which the file needs to be added and the location of the program file needs to be specified. Based on the extension of the file, XPS automatically adds it as a source or header.
R Chapter 2: Xilinx Platform Studio (XPS) Table 2-6: Options for commands xset_swapp_prop_value and xget_swapp_prop_value Option Name Description searchcomp Compiler Search Path Option (-B) searchlibs Library Search Path Option (-L) searchincl Include Search Path Option (-I) lflags Libraries to Link (-l) propopt Options passed down to the preprocessor (-Wp) asmopt Options passed down to the assembler (-Wa) linkopt Options passed down to the linker (-Wl) progstart Program Start Address st
R Chapter 3 Base System Builder The Base System Builder (BSB) wizard is a software tool that help users quickly build a working system targeted at a specific development board. Based on the user’s board selection, BSB will offer the user a number of options for creating a basic system on that board. These options include processor type, debug interface, cache configuration, memory type and size, and peripheral selection. For each option, functional default values will be preselected in the GUI.
R Chapter 3: Base System Builder Invoke BSB by selecting File o New Project o Base System Builder. . In the Create New Project dialog box, enter or browse to the directory where you would like to create a new XPS project. It is recommended that you start with a clean directory because any existing project files, including the .xmp, .mhs, and.mss files, may be overwritten when your new XPS project is being created.
R BSB Flow file is always created by default upon exit of the BSB wizard, reflecting the final selections of the current session. This feature may be useful to users who want to create several projects with similar designs. It is important to note that the .bsb settings file does not reflect any changes that users may make to their system outside of the Base System Builder wizard-- for example, if they add or edit cores from the XPS GUI or if they manually edit the MHS file.
R Chapter 3: Base System Builder Configuring Processor and System Settings Based the processor selected in the previous page, the user can configure certain system and processor specific settings. System settings include processor and bus clock frequencies. Allowable values may be restricted by the clock resources available on the target development board or the on-chip resources available in the FPGA device.
R BSB Flow . Selecting External Memories and I/O Devices The Base System Builder will determine what external memory and peripheral devices are available on your development board. For each device found, the user may indicate whether or not they want to use that device by clicking on the checkbox next to the device name. If a device interface is enabled, the user must select from a list of IP cores which can be used to control that device.
R Chapter 3: Base System Builder If you are unsure about what IP core to use, you may click the Data Sheet button on the right to view the data sheet of the currently selected core. Adding Internal Peripherals Internal peripherals are IP cores which do not communicate directly with any devices outside of the FPGA. Examples of such peripherals are on-chip memory (BRAM) controllers and timers.
R BSB Flow Configuring Software Settings The Base System Builder will generate a sample C application and linker script for the hardware system. This application is intended to verify system “aliveness” and also to provide an illustration of how to create a simple application. The contents of this program will depend on the hardware components which are included in the system as well as the options selected in this page.
R Chapter 3: Base System Builder The user may choose to not generate the sample application and linker script by deselecting the checkbox at the top of this page. Generating the System and Address Map Before generating the output files, the Base System Builder will display a summary of the system you have created. This page contains a table of IP cores which are instantiated in the system as well as the address map for these devices.
R BSB Flow Output Files The list of generated files are displayed on the final page of the Base System Builder Wizard. These files include x system.mhs: Microprocessor Hardware Specification file consisting of component instantiations, parameterization, and connections. x data/system.ucf: Xilinx User Constraints File containing constraints such as timing, FPGA pin locations, FPGA resource specification, and IO standards. x etc/fast_runtime.
R Chapter 3: Base System Builder Optional: x TestApp/src/TestApp.c: Sample application source file x TestApp/src/TestAppLnkScr: Linker script defining what memory locations to place each section of the application program in. x system.bsb: BSB specific settings file which can be loaded into a subsequent BSB session to automatically load the same GUI selections that were made in this session .
R Limitations Limitations The Base System Builder was designed for users who want to create a basic functional system quickly. As such, it does not allow users to create advanced systems or specify very specific configurations. The following are known limitations of the Base System Builder wizard: x BSB does not support multi-processor systems x BSB does not allow users to specify or modify the address map x BSB does not check for specific hardware resources on the target FPGA device.
R 76 Chapter 3: Base System Builder www.xilinx.com 1-800-255-7778 Embedded System Tools Guide (EDK 6.2i) UG111 (v1.
R Chapter 4 Create/Import Peripheral Wizard The Xilinx Embedded Design Kit (EDK) comes with a large number of commonly used peripherals. Many different kinds of systems can be created with these peripherals, but it is likely that you may have to create your own custom peripheral to implement functionality not available in the EDK peripherals library.
R Chapter 4: Create/Import Peripheral Wizard A EDK compliant peripherals. These have the following components: x A Bus Interface This is just a set of ports that the peripheral must have to connect to the targeted bus. x A component called the IP Interface (IPIF) The bus interface connects to this component. Additionally, it provides a lot of functionality that most EDK compliant peripherals need. These include address decoding, addressable registers, interrupt handling, DMA support, etc.
R Creating New Peripherals EDK repository is the more versatile storage mechanism because many XPS projects can access one EDK repository. This tool takes care of creating the right directory structures and interface files. In this panel, you indicate whether you want a XPS project or EDK repository, and what the physical location of the XPS project or EDK repository is. A XPS project is a directory with a .xmp file. A EDK repository is a directory.
R Chapter 4: Create/Import Peripheral Wizard Figure 4-2: Module Name and Version Select Bus Interface In this panel you indicate the CoreConnect bus-interface, i.e. if your peripheral is a fast (but more complicated) PLB (Processor Local Bus) or a comparatively simpler and slower OPB (on-chip peripheral bus) peripheral. For the present, only slave type peripherals are supported. Master type peripherals will be supported in a future release.
R Creating New Peripherals Figure 4-4: Select IPIF Services The IPIF provides some very basic services like slave attachment, address decoding, byte steering, and some optional services that may greatly simplify the task of creating your peripheral. These features are described in Table 4-3: IPIF Services IPIF Feature Description Include Software Reset and Module Information registers The peripheral will have a special write only address.
R Chapter 4: Create/Import Peripheral Wizard Table 4-3: IPIF Services IPIF Feature Description Include Software Addressable Registers in user-logic The user-logic part of the peripheral will have registers addressable through software. Include Address Range Support in user-logic This will generate enable signals for each address range. This feature is useful for peripherals that need to support multiple address ranges, e.g. multiple memory banks.
R Creating New Peripherals processed in conjunction with the interrupts generated out of the other IPIF services. The IP ISC has a software addressable interrupt enable register (IP IER) that may be used to enable/disable interrupts from the software application. Both the IP ISC and ‘device’ ISC are implemented in the IPIF component of the core. In this panel, you will have to indicate the number of interrupts generated by the userlogic, and the capture mode of these interrupts.
R Chapter 4: Create/Import Peripheral Wizard Note that the peripheral is sometimes referred to as a ‘device’ in this tool and associated documentation. ‘Device’ just refers to the peripheral in question, not the FPGA! Additionally, it is important to understand that the interrupts discussed here are processed by the IPIF, not directly by the interrupt controller processing the interrupts sent to the processor.
R Creating New Peripherals Figure 4-7: Configure Address Ranges You will need to indicate the number of address ranges, and the size (byte, half-word and word) of the data being accessed. We recommend the size of these registers be the same as the data-width of the bus to which it is connected, 32 bits for OPB peripherals and 64 bits for PLB peripherals. This will allow for a smaller implementation of the IPIF by optimizing out the implementation of the byte-steering logic.
R Chapter 4: Create/Import Peripheral Wizard Some of the IPIC ports in this panel are already selected and cannot be deselected. These ports are required to implement the functionality indicated in the Select IPIF Services panel. Figure 4-9: Review the EDK Peripheral Design Flow Review EDK Peripheral Design Flow After all the input has been entered, the following files are created: x core_name.vhd x user_logic.vhd Here core_name.vhd implements the ‘top’ module core_name of your peripheral.
R Importing an Existing Peripheral understand how to address the registers and interpret the data available there. These are documented in the IPIF section of the Processor IP Document. You should create a simple test system and implement and simulate that using the various flows available in the EDK. Generating the files representing your peripheral Once all the required data has been collected from the user, this tool does the following: x Creates HDL files described above.
R Chapter 4: Create/Import Peripheral Wizard Identifying Module and Version This is identical to the functionality described under “Identifying Module and Version” in the “Creating New Peripherals” section. Select Source File Types In this panel you indicate the kinds of files that make up your peripheral. Presently, the system requires you to have at least one HDL file in VHDL or Verilog with the .vhd or .v extensions respectively. Your peripheral may also instantiate black box netlists.
R Importing an Existing Peripheral Please ensure that filename does not have any spaces. Such path names are not supported at the present time. The top-level HDL source file is expected to conform to the Xilinx implementation of the CoreConnect Bus Conventions. Please review OPB/PLB usage in Chapter 1 and 2 of the Processor IP User Guide found in the doc directory in the install.
R Chapter 4: Create/Import Peripheral Wizard Figure 4-13: Indicating HDL Analysis Information by Browsing to Files If you had chosen to select files by using the file browser, you can use the Move File Up and Move File Down buttons to change the compile order of the files. Typically a selected file is assumed to be compiled into the logical library containing the current peripheral. This was explained in the “Identifying Module and Version” section.
R Importing an Existing Peripheral After you exit the Select Library panel, you are returned back to the HDL Analysis Information panel where the newly selected files are displayed. Figure 4-15: Select bus Interfaces Bus Interfaces In this panel you indicate the types of bus interfaces that your peripheral supports.
R Chapter 4: Create/Import Peripheral Wizard Identifying Bus Interface Ports and Parameters A peripheral that implements a particular bus interface needs to the have the ports required by that interface. The ports do not have to have specific names, but it is best if the port are named exactly as specified in the specification of that interface. When the ports are named as the convention requires, this tool will correctly identify the bus interface ports.
R Importing an Existing Peripheral port have drop-down lists that list the ports on the peripheral being imported. The user needs to select the peripheral port which corresponds to each bus-interface port. Interrupt Signals Each peripheral needs to identify its interrupt signals and certain special attributes associated with the interrupt. These interrupts are processed by the interrupt controller in the processor system.
R Chapter 4: Create/Import Peripheral Wizard x The one-column table on the left lists the ports identified by this tool. A drop-down list on the top of the table allows you to list bus interface ports only, or user (non-bus interface) ports only, or list all ports. The structure is very similar for the parameters. x The table to the right has two columns. The column on the left lists the attributes and the one on the right displays the values of the corresponding attributes.
R Importing an Existing Peripheral If you position the cursor on one of the attributes in the left column of the Attributes Table, a short description of the attribute will appear. This description will usually contain the MPD keyword for this parameter. Figure 4-20: Setting Attributes on Parameters Netlist files Your peripheral can be HDL with fixed netlists instantiated as black-boxes. In this panel you locate the netlist files associated with your peripheral.
R Chapter 4: Create/Import Peripheral Wizard Documentation files Documentation files are selected by browsing to the file. These files can be in any of the common formats, e.g. PDF (.pdf) or TEXT (.txt). Figure 4-22: Select Documentation Files Finishing Peripheral Import Once all the required data has been collected from the user, this tool does the following: x Copy over the user HDL, netlist and documentation files into the XPS project into a directory structure determined by the PSF specification.
R Organization of generated files Organization of generated files This tool generates files based on user input. Table 4-5 describes what files are generated and how they are used.
R Chapter 4: Create/Import Peripheral Wizard Table 4-5: Files and directories generated by the Create/Import IP Wizard Directory or file Description /_xst.prj XST project file. In case you add more files HDL to your peripheral, you need to add them to this file. /_xst.scr A simple XST script file that uses the XST project file and can be passed to XST to generate the netlist representing the peripheral.
R Chapter 5 Platform Generator The hardware component is defined by the Microprocessor Hardware Specification (MHS) file. An MHS file defines the configuration of the embedded processor system, and includes the following: x Bus architecture x Peripherals x Connectivity of the system x Interrupt request priorities x Address space Hardware generation is done with the Platform Generator (PlatGen) tool and an MHS file.
R Chapter 5: Platform Generator Tool Options The following are the options supported in the current version: -h (Help) The -h option displays the usage menu and quits. -v (Display version) The -v option displays the version and quits. -f Read command line arguments and options from file. -iobuf yes|no IOB insertion at the top-level. The default is yes. This option is deprecated. Please use the ’-toplevel’ option. -lang verilog|vhdl HDL language output. The default is vhdl. -log
R Load Path Load Path Refer to Figure 5-1 for a depiction of the peripheral directory structure. To specify additional directories, use one of the following options: x Current directory (where PlatGen was launched; not where the MHS resides) x Set the EDK tool option -lp option PlatGen uses a search priority mechanism to locate peripherals, as follows: 1. Search the pcores directory in the project directory 2. Search //pcores as specified by the -lp option 3.
R Chapter 5: Platform Generator system_stub.[vhd|v] This is the toplevel template HDL file of the instantiation of the system and IOB primitives. Use this file as a starting point for your own toplevel HDL file. This file is generated when the -toplevel no option is specified. Othewise, the system.[vhd|v] file is the toplevel. _wrapper.[vhd|v] This is the HDL wrapper file for the of individual IP components defined in the MHS.
R About Memory Generation and a PLB BRAM controller to the same BRAM block instance. You can connect a LMB BRAM controller and a DSOCM BRAM controller to the same BRAM block instance. The BRAM controller’s MHS options, C_BASEADDR and C_HIGHADDR (see Chapter 15, “Microprocessor Hardware Specification (MHS),” for more information), define the different depth sizes of memory. The MicroBlaze processor is a 32-bit machine, therefore, has data and instruction bus widths of 32-bit.
R Chapter 5: Platform Generator BMM Flow The EDK tools Implementation Tools flow using Data2MEM. ngdbuild -bm .bmm .ngc map par bitgen -bd .elf BitGen outputs _bd.bmm that contains the physical location of BlockRAMs. The _bd.bmm and .bit files are input to Data2MEM. Data2MEM translates contiguous fragments of data into the proper initialization records for Virtex series BlockRAMs.
R Synthesis Netlist Cache Table 5-2: Automatically Expanded Reserved Parameters Parameter Description C_OPB_NUM_SLAVES Number of OPB slaves C_PLB_AWIDTH PLB Address width C_PLB_DWIDTH PLB Data width C_PLB_MID_WIDTH PLB master ID width C_PLB_NUM_MASTERS Number of PLB masters C_PLB_NUM_SLAVES Number of PLB slaves Synthesis Netlist Cache An IP rebuild occurs with one of the following fundamental changes: x Instance name change x Parameter value change x Core version change x Core is sp
R 106 Chapter 5: Platform Generator www.xilinx.com 1-800-255-7778 Embedded System Tools Guide (EDK 6.2i) UG111 (v1.
R Chapter 6 Simulation Model Generator This chapter introduces the basics of HDL simulation and describes the Simulation Model Generator tool and COMPEDKLIB utility usage. It contains the following sections.
R Chapter 6: Simulation Model Generator Simulation Basics This section introduces the basic facts and terminology of HDL simulation in EDK. There are three stages in the FPGA design process in which you conduct verification through simulation. Figure 6-1 shows these stages.
R Compiling EDK Simulation Libraries UNISIM Library This is a library of functional models used for behavioral and structural simulation. It contains default unit delays and includes all of the Xilinx Unified Library components that are inferred by most popular synthesis tools. The UNISIM library also includes components that are commonly instantiated such as I/Os and memory cells.
R Chapter 6: Simulation Model Generator To print the COMPEDKLIB online help to your monitor screen, type the following at the command line: compedklib -h COMPEDKLIB Command Line Examples Use Case I: Compiling HDL sources in the built-in repositories in the EDK The most common use case is as follows: compedklib -o -X In this case the pcores available in the EDK install are compiled and the stored in .
R Simulation Models Behavioral Models To create a behavioral simulation model, SimGen requires an MHS file as input. SimGen will create a set of hdl files that model the functionality of the design. Optionally, SimGen can generate a compile script for a specified vendor simulator. Also not required but if specified, SimGen can generate hdl files with data to initialize brams associated with any processor that may exist in the design. This data is obtained from an existing executable elf file.
R Chapter 6: Simulation Model Generator Timing Models To create a timing simulation model, SimGen requires an MHS file as input and associated implemented netlist file. From this netlist file SimGen will create an hdl file that models the design and an SDF file with appropriate timing information for it. Optionally, SimGen can generate a compile script for a specified vendor simulator.
R SimGen Syntax Options file -f Read command line arguments and options from file HDL Language -lang vhdl|verilog The -lang option specifies the HDL Language. Default: vhdl Log output -log The -log option specifies the log file. Default: simgen.log Library Directories -lp The -lp option allows you to specify library directory paths. This option may be specified more than once for multiple library directories.
R Chapter 6: Simulation Model Generator Simulator -s mti | ncs Generate compile script for vendor simulator. mti - ModelSim ncs - NcSim Source Directory -sd Source directory to search for netlist files. Top-level Instance -ti When design represents a submodule, use top_instance for the top-level instance name. This swithc is only valid when the “-toplevel no” switch is used.
R Memory Initialization After a successful simgen execution, the simulation directory contains the following files: peripheral_wrapper.[vhd|v] Modular simulation files for each component. Not applicable for timing models. system_name.[vhd|v] The top level HDL file of the design. system_name.sdf The Standard Delay Format file with the appropriate block and net delays from the place and route process used only for timing simulation. system_name.
R Chapter 6: Simulation Model Generator “Verifying Your Design” in the ISE Synthesis and Verification Design Guide for more information. A PDF version of this document can be found at /doc/usenglish/books/docs/sim/sim.pdf in your XILINX install area, or online at http://www.xilinx.com/support/sw_manuals/xilinx6/index.htm Current Limitations SimGen does not support generation of mixed level simulation models. 116 www.xilinx.com 1-800-255-7778 Embedded System Tools Guide (EDK 6.2i) UG111 (v1.
R Chapter 7 Library Generator This chapter describes the Library Generator (LibGen) utility needed for the generation of libraries and drivers for embedded soft processors. It also describes how the user can customize peripherals and associated drivers.
R Chapter 7: Library Generator Tool Options The following options are supported in this version: -h, -help (Help) This option causes LibGen to display the usage menu and exit. -v (display version information) This option displays the version number of LibGen. -log logfile[.log] This option specifies the log file. The default is libgen.log. -p family_name (architecture family) This option defines the target architecture family. Use -h option to get a list of values for Family_name.
R Tool Options x If no HW_SPEC_FILE parameter is found in the MSS file, use the base name mssfile (name without .mss extension) with the .mhs extension as the mhsfilename. -mode Specifies the following modes for all processor instances in the MSS file. -mode executable: This mode should be employed if the user wants to generate a stand-alone executable program for all processor instances. The EXECUTABLE attribute in the MSS file is used in this mode.
R Chapter 7: Library Generator Note: This option is DEPRECATED. Use XPS for intializing BRAMs with executable information (refer to Chapter 2, “Xilinx Platform Studio (XPS)”). The bram_init.sh file is no longer used to intialize the bitstream with executable information.
R Load Path To specify additional directories, use one of the following options: x Current working directory from which LibGen was launched. x Set the EDK tool option -lp. LibGen looks for drivers, OS’s and libraries under each of the subdirectories of the path specified in the -lp option. LibGen uses a search priority mechanism to locate drivers/libraries, as follows: 1. 2. 3. Searching the current working directory: a.
R Chapter 7: Library Generator drivers sw_services bsp pcores src .c files data .h files MDD src Tcl .c files data .h files MLD src Tcl .c files data .h files MLD src Tcl .c files data .h files MDD Tcl X10134 Figure 7-2: Directory Structure of Drivers, OS’s and Libraries Output Files LibGen generates directories and files in the USER_PROJECT directory.
R Libraries and Drivers Generation directories. Refer to the “Drivers”, “OS”, and “Libraries” sections of this chapter for more information. code directory The code directory is a repository for EDK executables. LibGen creates xmdstub.elf (for MicroBlaze on-board debug) in this directory. Note: LibGen removes all the above directories everytime the tool is run. Users must put in their sources/executables or any other files in a user created area.
R Chapter 7: Library Generator For more information about the Tcl procedures and MDD/MLD related parameters, refer to chapter Chapter 21, “Microprocessor Driver Definition (MDD)” and Chapter 20, “Microprocessor Library Definition (MLD)”. MSS Parameters For a complete description of the MSS format and all the parameters that MSS supports, refer to Chapter 19, “Microprocessor Software Specification (MSS)”. Drivers Most peripherals require software drivers.
R OS should have the targets “include” and “libs”. Each library must also contain an MLD file and a Tcl file in the data subdirectory. Refer to the existing EDK libraries to get an understanding of the structure of the libraries. Refer to Chapter 20, “Microprocessor Library Definition (MLD)” for details on how to write an MLD and its corresponding Tcl file. OS The MSS file now includes an OS block for each processor instance.
R Chapter 7: Library Generator XMDSTUB Peripherals (MicroBlaze Specific) These are peripherals that are used specifically for debug with the xmdstub program (For more information about the debug program xmdstub, refer to Chapter 13, “Xilinx Microprocessor Debugger (XMD)”). The attribute XMDSTUB_PERIPHERAL is used for denoting the debug peripheral instance. LibGen uses this attribute to generate the debug program xmdstub.
R Chapter 8 Platform Specification Utility This chapter describes the various features and the usage of the Platform Specification Utility (PsfUtil) tool that enables automatic generation of Microprocessor Peripheral Description files (MPD) required to create an IP core compliant with the Embedded Development Kit (EDK). Many of these features may be used with the help of wizards in the Xilinx Platform Studio (XPS) GUI tool. This chapter contains the following sections.
R Chapter 8: Platform Specification Utility -o Specify output filename, Default : stdout -pao2mpd Generate MPD from Peripheral Analyze Order (PAO) file.
R Detailed Use Models for Automatic MPD Creation x OPB MASTER_SLAVE x PLB SLAVE x PLB MASTER x PLB MASTER_SLAVE x DCR SLAVE x LMB SLAVE x TRANSPARENT BUS (special case) Peripherals with a Single Bus Interface Majority of processor peripherals fall into this category. This is also the simplest usage model for PsfUtility. For most peripherals, complete MPD specifications can be obtained without specification of any additional attributes in the source code.
R Chapter 8: Platform Specification Utility Non-Exclusive Bus Interfaces Signal Naming Conventions The signal names must follow conventions as specified in the VHDL Peripheral Description Guide. For non-exclusive bus interfaces, bus identifiers need not be specified for the bus signals. Invoking PsfUtility with buses specified in command line Buses can be specified on the command line when the bus signals are not prefixed with bus identifiers.
R About Specification of VHDL Attributes Note that the BRAM ports should follow signal naming conventions as specified in the VHDL Peripheral Definition document. About Specification of VHDL Attributes The MPD format of EDK consists of additional sub-properties that are required for successful Platform Generation.
R Chapter 8: Platform Specification Utility Properties on Ports Port Value When signal naming conventions are followed, PsfUtility automatically connects the bus signals to the appropriate bus connector. DIR This value is automatically generated by PsfUtility. VEC This value is automatically generated by PsfUtility. BUSIF When signal naming conventions are followed, PsfUtility automatically associates a BUS with a port. For transparent buses however, the BUSIF attribute MUST BE SPECIFIED for the port.
R DRC Checks in PsfUtility Properties on Parameters MIN_SIZE (for Address parameter - User MUST specify) Specifies the minimum size in words of the peripheral address space ADDRESS and PAIR (for address parameter) ADDRESS can take the values BASE, HIGH, SIZE or NONE. Specifies whether parameter is base or high address or not an address at all. All parameters ending with _BASEADDR will be assigned ADDRESS=BASE. All parameters ending with _HIGHADDR will be assigned ADDRESS=HIGH.
R Chapter 8: Platform Specification Utility x Check and report any repeated Bus Signals for every specified bus interface PsfUtility will not generate an MPD unless all bus interface checks are completed. Verilog Language Support PsfUtility supports Verilog language as well. Currently, there exists no means for specifying attributes of ports/parameters in Verilog. VHDL Peripheral Definitions The top-level VHDL source file for an IP core defines the interface of the design.
R VHDL Peripheral Definitions Table 8-1: Recognized Bus Interfaces Description Bus label in MPD Master OPB interface MOPB Master/slave OPB interface MSOPB Slave OPB interface SOPB Master PLB interface MPLB Master/slave PLB interface MSPLB Slave PLB interface SPLB For components that have more than one bus interface of the same type, a naming convention must be followed so that the automation tools can group the bus interfaces.
R Chapter 8: Platform Specification Utility errors when your peripheral requires information on the platform that is generated.
R VHDL Peripheral Definitions C_FAMILY The C_FAMILY parameter defines the FPGA device family. This parameter is automatically populated by Platform Generator. C_INSTANCE The C_INSTANCE parameter defines the instance name of the component. This parameter is automatically populated by Platform Generator. C_OPB_NUM_MASTERS The C_OPB_NUM_MASTERS parameter defines the number of OPB masters on the bus. This parameter is automatically populated by Platform Generator.
R Chapter 8: Platform Specification Utility C_OPB_DWIDTH The C_OPB_DWIDTH parameter defines the OPB data width. This parameter is automatically populated by Platform Generator. C_OPB_NUM_MASTERS The C_OPB_NUM_MASTERS parameter defines the number of OPB masters on the bus. This parameter is automatically populated by Platform Generator. C_OPB_NUM_SLAVES The C_OPB_NUM_SLAVES parameter defines the number of OPB slaves on the bus. This parameter is automatically populated by Platform Generator.
R VHDL Peripheral Definitions x If more than one instance of a particular bus interface type is used on a core, a bus identifier, , must be used in the signal identifier. The bus identifier can be as simple as a single letter or as complex as a descriptive string with a trailing underscore. The must be included in the port’s signal identifiers in the following cases: i The core has more than one slave PLB port. i The core has more than one master PLB port.
R Chapter 8: Platform Specification Utility x is a Bus Identifier; it is optional for peripherals with a single slave DCR port, and required for peripherals with multiple slave DCR ports. must not contain the string, “DCR” (upper or lower case or mixed case). For peripherals with multiple slave DCR ports, the strings must be unique for each bus interface. x If is present, then is optional.
R VHDL Peripheral Definitions _Ready : out std_logic; Examples: D_Ready : out std_logic; I_Ready : out std_logic; LMB Slave Inputs For interconnection to the LMB, all slaves must provide the following inputs: _ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); _AddrStrobe : in std_logic; _BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1); _Clk : in std_logic; _ReadStrobe : in std_logic; _Rst : in std_logic; _WriteDBus : i
R Chapter 8: Platform Specification Utility IM_request : out std_logic; Bridge_request : out std_logic; O2Ob_request : out std_logic; OPB Master Inputs For interconnection to the OPB, all masters must provide the following inputs: _Clk _DBus _errAck _MGrant _retry _Rst _timeout _xferAck : : : : : : : : in in in in in in in in std_logic; std_logic_vector(0 to C_OPB_DWIDTH-1); std_logic; std_logic; std_logic; std_logic;
R VHDL Peripheral Definitions OPB Slave Inputs For interconnection to the OPB, all slaves must provide the following inputs: _ABus _BE _Clk _DBus _Rst _RNW _select _seqAddr : : : : : : : : in in in in in in in in std_logic_vector(0 to C_OPB_AWIDTH-1); std_logic_vector(0 to C_OPB_DWIDTH/8-1); std_logic; std_logic_vector(0 to C_OPB_DWIDTH-1); std_logic; std_logic; std_logic; std_logic; Examples: OPB_DBus IOPB_DBu
R Chapter 8: Platform Specification Utility _errAck _retry _toutSup _xferAck : : : : out out out out std_logic; std_logic; std_logic; std_logic; Examples: IM_request : out std_logic; Bridge_request : out std_logic; O2Ob_request : out std_logic; OPB Master/Slave Inputs For interconnection to the OPB, all master/slaves must provide the following inputs: _ABus _BE _Clk _DBus _errAck _MGrant _retry <
R VHDL Peripheral Definitions _busLock _compress _guarded _lockErr _MSize _ordered _priority _rdBurst _request _size _type _wrBurst _wrDBus : : : : : : : : : : : : : out out out out out out out out out out out out out std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic_vector(0 std_logic; std_logic; std_logic_vector(0 std_logic_vector(0 std_logic; std_logic_vector(0 to 1); t
R Chapter 8: Platform Specification Utility PLB Slave Outputs For interconnection to the PLB, all slaves must provide the following outputs: _addrAck : _MErr _MBusy : _rdBTerm _rdComp _rdDAck _rdDBus _rdWdAddr _rearbitrate _SSize _wait _wrBTerm _wrComp _wrDAck : out std_logic; out std_logic_vector(0 to C_PLB_NUM_MASTERS-1); out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
R VHDL Peripheral Definitions Entity-level VHDL Attributes for Automation Support Table 8-2: Entity-level VHDL Attributes Type Values Default PsfUtil Automation integer - X - Address slice of BRAM controller integer - X - Address width of BRAM controller ALERT string - X - Alert message CORE_STATE string ACTIVE ACTIVE - Core state Attribute ADDR_SLICE AWIDTH Definition DEPRECATED OBSOLETE DEVELOPMENT BUSID DWIDTH HDL string - X - Bus Identifier string for cores using the
R Table 8-2: Chapter 8: Platform Specification Utility Entity-level VHDL Attributes Type Values Default PsfUtil Automation PAY_CORE string X - Specifies the license key value for a Pay Core RUN_NGCBUILD string TRUE FALSE - Run NgcBuild to merge all netlists for designs specified as a mix of netlists and HDL X - Special class of components that require special handling HDL - Design style X - Top-level name Attribute FALSE SPECIAL string BRAM BRAM_CNTLR STYLE st
R VHDL Peripheral Definitions ADDR_SLICE Attribute The address slice position supported by the BRAM controller is specified by the ADDR_SLICE attribute. Format attribute ADDR_SLICE : integer; attribute ADDR_SLICE of Peripheral:entity is 29; Used only by components of SPECIAL=BRAM_CNTLR. AWIDTH Attribute The address width supported by the BRAM controller is specified by the AWIDTH attribute.
R Chapter 8: Platform Specification Utility attribute BUSID of Peripheral:entity is "S:OPB_SLAVE:OPB_MASTER_SLAVE"; attribute BUSID : string; attribute BUSID of Peripheral:entity is "S:OPB_SLAVE:OPB_MASTER_SLAVE,M:OPB_MASTER"; The BUSID attribute must be used when a bus that is used by the core uses the optional field in the names associated with the bus.
R VHDL Peripheral Definitions ... attribute BUSID : string; attribute BUSID of Peripheral:entity is "A:OPB_SLAVE,B:OPB_SLAVE"; CORE_STATE Attribute The state of the IP core is specified with the CORE_STATE attribute. Format attribute CORE_STATE : string; attribute CORE_STATE of Peripheral:entity is "ACTIVE"; The following values are valid: x ACTIVE - Core is active (full uninhibited use) by EDK. This is the default setting. x DEPRECATED - Core is deprecated.
R Chapter 8: Platform Specification Utility Format attribute IMP_NETLIST : string; attribute IMP_NETLIST of Peripheral:entity is TRUE; IPTYPE Attribute The IPTYPE attribute lists defines the type of the component. PsfUtility automatically sets the value to PERIPHERAL if not otherwise specified.
R VHDL Peripheral Definitions For a byte-write 32-bit data memory, the NUM_WRITE_ENABLES = 4. For a byte-write 64bit data memory, the NUM_WRITE_ENABLES = 8. Used only by components of SPECIAL=BRAM_CNTLR. PAY_CORE Attribute The PAY_CORE attribute defines the value of the license value to be used for for all pay cores. Format attribute PAY_CORE : string; attribute PAY_CORE of Peripheral:entity is "my_lic_val"; This attribute is reserved for internal use only.
R Chapter 8: Platform Specification Utility attribute STYLE of Peripheral:entity is value; Where value is BLACKBOX, MIX, or HDL. The default value is HDL. Generic-level VHDL Attributes for Automation Support Table 8-3: Generic-level VHDL Attributes PsfUtil Automation Attribute Type Values Default Definition MIN_SIZE string 2n in hexadecimal notation 0 - Minimum size address window; format is a string representing a Cstyle hexadecimal number.
R VHDL Peripheral Definitions attribute MIN_SIZE : string; attribute MIN_SIZE of C_BASEADDR:constant is "0x100"; end entity Peripheral; ADDRESS and PAIR Attribute The address type of an address parameter is specified by attaching a ADDRESS attribute to the _BASEADDR or _HIGHADDR generic. The default ADDRESS attribute for all signals that end with _BASEADDR is BASE, and the default value for all signals that end with _HIGHADDR is HIGH.
R Chapter 8: Platform Specification Utility Signal-level VHDL Attributes for Automation Support Table 8-4: Signal-level VHDL Attributes Attribute THREE_STATE Type string Values Default TRUE X string BUF 3-state expansion (equivalent to the 3STATE parameter in MPD file) INFER - Identifies ports that instantiate or infer IOB primitives X - Signal classification Semi-automatic inference when ranges can be resolved at compile time Specifies endianess of signals.
R VHDL Peripheral Definitions port ( PAR_I : in std_logic; PAR_O : out std_logic; PAR_T : out std_logic; ); attribute THREE_STATE : string; attribute THREE_STATE of PAR_I:signal is "FALSE"; attribute THREE_STATE of PAR_O:signal is "FALSE"; attribute THREE_STATE of PAR_T:signal is "FALSE"; end entity Peripheral; IOB_STATE Attribute The IOB_STATE attribute identifies ports that instantiate or infer IOB primitives.
R Chapter 8: Platform Specification Utility x INTR_LEVEL_LOW: indicating it is an Interrupt signal with Level Low Sensitivity x INTR_EDGE_RISING: indicating it is an Intr signal sensitive on rising edge x INTR_EDGE_FALLING: indicating it is an Intr signal sensitive on falling edge x RST: indicating it is a Reset signal INITIALVAL Attribute This specifies the Initial Value on a signal if it is unconnected.
R Chapter 9 Format Revision Tool Revup from EDK 6.1 to EDK 6.2 The Format Revision Tool (revup) updates an existing EDK 6.1 project to a format for EDK 6.2. Note that if you open a EDK 6.1 project in XPS 6.2, then it will automatically revup the project to the new format. If you have a project which is from EDK release 3.2 or 3.1, XPS will not update that project. You must update the project yourself from the command line shell using revup32to61 utility. Please refer to section “Revup from EDK 3.
R Chapter 9: Format Revision Tool Revup from EDK 3.2 to EDK 6.1 The Format Revision Tool (revup32to61) updates an existing EDK 3.1 or 3.2 project to a format for EDK 6.1. Note that if you open an old project with XPS, then it will automatically revup the project to the new format. A project revup will also automatically cause revup of all the hardware repository data files (MPD, BBD, and PAO) referred to by that project and that of the local myip and pcores directories.
R Chapter 10 Bitstream Initializer This chapter describes the Bitstream Initializer (BitInit) utility. The chapter contains the following sections. x “Overview” x “Tool Usage” x “Tool Options” Overview The Bitstream Initializer tool initializes the instruction memory of processors on the FPGA. The instruction memory of processors are stored in BlockRAMs in the FPGA. This utility reads an MHS file, and invokes the Data2MEM utility provided in ISE to initialize the FPGA BlockRAMs.
R Chapter 10: Bitstream Initializer Default: implementation/.bit -o (Output Bitstream file) The -o option specifies the name of the output file to generate the bistream with initialized memory. Default: implementation/download.bit -pe (Specify the Processor Instance name and list of elf files) The -pe option specifies the name of the processor instance in the MHS and it’s associate list of ELF files that form it’s instruction memory.
R Chapter 11 GNU Compiler Tools This chapter describes the various options supported by MicroBlaze and PowerPC GNU tools. The MicroBlaze GNU tools include mb-gcc compiler, mb-as assembler and mb-ld loader/linker. The PowerPC tools include powerpc-eabi-gcc compiler, powerpc-eabi-as assembler and the powerpc-eabi-ld linker. The EDK GNU tools also support C++. This chapter discusses only those options which have been added or enhanced for the Embedded Development Kit (EDK).
R Chapter 11: GNU Compiler Tools GNU Compiler Framework Input C/C++ Files cpp0 cc1 cc1plus as (mb-as or powerpc-eabi-as) ld Libraries (mb-ld or powerpc-eabi-ld) Output Elf File UG111_05_120103 Figure 11-1: GNU Tool Flow 164 www.xilinx.com 1-800-255-7778 Embedded System Tools Guide (EDK 6.2i) UG111 (v1.
R Compiler Usage and Options This section discusses the common features of both the MicroBlaze as well as PowerPC compiler. Figure 11-1 shows the GNU tool flow. The GNU compiler is named mb-gcc for MicroBlaze and powerpc-eabi-gcc for PowerPC. The GNU compiler is a wrapper which in turn calls four different executables: 1. 2. 3. 4. Pre-processor: (cpp0) i This is the first pass invoked by the compiler.
R Table 11-1: Chapter 11: GNU Compiler Tools Commonly Used Compiler Options Options Explanation -E Preprocess only; Do not compile, assemble and link. The preprocessed output is displayed on the standard out device -S Compile only; Do not assemble and link (Generates .s file) -c Compile and Assemble only; Do not link (Generates .o file) -g Add debugging information, which is used by GNU debugger (mb-gdb or powerpc-eabi-gdb) -gstabs Add debugging information to the compiled assembly file.
R Compiler Usage and Options -On The GNU compiler provides optimizations at different levels. These optimization levels are applied only to the C and C++ source files. Table 11-2: Optimizations for different values of n n Optimization 0 No Optimization 1 Medium Optimization 2 Full optimization 3 full optimization, and also attempt automatic inlining of small subprograms. S Optimize for speed Note: Optimization levels 1 and above will cause code re-arrangement.
R Chapter 11: GNU Compiler Tools There are certain options which are required by tool, but might not be necessary for the top level compiler.
R Compiler Usage and Options Linker Options -defsym _STACK_SIZE=value The total memory allocated for the stack and the heap can be modified by using the above linker option. The variable STACK_SIZE is the total space allocated for heap as well as the stack. The variable STACK_SIZE is given the default value of 100 words (i.e 400 bytes).
R Chapter 11: GNU Compiler Tools Initialization files are searched in the following order (1): 1. Directories passed to the compiler with the -B dir name option. 2. ${XILINX_EDK}/gnu/processor/sol/processor/lib On Windows Xygwin Shell The GNU compilers (mb-gcc and powerpc-eabi-gcc) search certain paths for libraries and header files. Libraries are searched in the following order: 1. Directories passed to the compiler with the -L dir name option. 2.
R Compiler Interface Table 11-4: File Extensions Extension File type .S Assembly File, but might have preprocessor directives .s Assembly File with no preprocessor directives Libraries Both the compiler (powerpc-eabi-gcc and mb-gcc) use certain libraries. The following libraries are needed for all the program. Table 11-5: Libraries used by the compilers Library Particular libxil.
R Chapter 11: GNU Compiler Tools x Preprocessor output (.i or .ii file) (if -save-temps option is used) MicroBlaze GNU Compiler The MicroBlaze GNU compiler is an enhancement over the standard GNU tools and hence provides some additional options, which are specific to the MicroBlaze system.These options are available only in the MicroBlaze GNU compiler. Quick Reference Table 11-6: MicroBlaze Specific Options Options Explanation -xl-mode-executable Default mode for compilation.
R MicroBlaze GNU Compiler multiplier gives better performance, but can be done only on devices with hardware multiplier such as Virtex II. -mxl-soft-div The MicroBlaze processor does not come with a hardware divide unit. The users would need the software routine in the libraries for the divide operation. This option is turned on by default in mb-gcc. -mno-xl-soft-div In MicroBlaze version 2.00 and beyond, the user can instantiate a hardware divide unit in MicroBlaze.
R Chapter 11: GNU Compiler Tools -xl-mode-xmdstub Xilinx Microprocessor Debugger (XMD) allows three different modes of debugging an user program for MicroBlaze. The three debugging options are x Simulator mode (Does not require a board) x XMDStub mode (Requires the XMDStub to be a part of the bitstream) x MDM mode (Hardware debugging enabled. Bitstream does not contain the XMDStub) For more information about the XMD tool, refer to the , “Xilinx Microprocessor Debugger (XMD)” chapter in the guide.
R MicroBlaze GNU Compiler where mytargetlabel is the label of the target instruction. The mb-as assembler computes the immediate value of the instruction as mytargetlabel - PC. If this immediate value is greater than 16 bits, the mb-assembler automatically inserts an imm instruction. If the value of mytargetlabel is not known at the time of compilation, the mb-as assembler always inserts an imm instruction.
R Chapter 11: GNU Compiler Tools -relax This is a linker option, used to remove all the unwanted imm instructions generated by the assembler. The assembler generates imm instruction for every instruction where the value of the immediate can not be calculated during the assembler phase. Most of these instructions won’t need an imm instruction. These are removed by the linker when the relax command line option is provided to the linker. This option is required only when linker is invoked on its own.
R MicroBlaze GNU Compiler object files instead of the standard files, use the -B directory-name command line option while invoking mb-gcc. According to the C standard specification, all global and static variables need to be initialized to 0. This is a common functionality required by all the crt’s above. Hence another routine _crtinit is defined in crtinit.o file. This file is part of the libc.a library.
R Chapter 11: GNU Compiler Tools Table 11-8: Use of attributes Attributes Functions interrupt_handler This attribute saves the machine status register and all the volatiles in addition to the non-volatile registers. rtid is used for returning from the interrupt handler. If the interrupt handler function is a leaf function, only those volatiles which are used by the function are saved.
R Chapter 12 GNU Debugger This chapter describes the general usage of the Xilinx GNU debugger for MicroBlaze and PowerPC. The chapter contains the following sections. x “Overview” x “Tool Usage” x “Tool Options” x “MicroBlaze GDB Targets” x “PowerPC Targets” x “GDB Command Reference” Overview GDB is a powerful yet flexible tool which provides a unified interface for debugging/verifying MicroBlaze and PowerPC systems during various development phases. Embedded System Tools Guide (EDK 6.
R Chapter 12: GNU Debugger GDB mb-gdb or PowerPC-eabi-gdb Tcl/Terminal Interface GDB Remote Protocol (TCP/IP) XMD PowerPC Hardware Board MicroBlaze Instruction Set Simulator MicroBlaze Hardware Board X9987 Figure 12-1: GDB Debugging Using XMD Tool Usage MicroBlaze GDB usage: mb-gdb [options] [executable-file] PowerPC GDB usage: powerpc-eabi-gdb [options] [executable-file] Tool Options The most common options in the MicroBlaze GNU debugger are: --command=FILE Execute GDB commands from FILE.
R MicroBlaze GDB Targets --nw Do not use a GUI interface. -w Use a GUI interface. (Default) MicroBlaze GDB Targets Currently, there are three possible targets that are supported by the MicroBlaze GNU Debugger and XMD tools - a built-in simulator target and two remote targets (XMD): xilinx > mb-gdb hello_world.elf From the Run pull-down menu, select Connect to target in the mb-gdb window. In the Target Selection dialog, you can choose between the Simulator (built-in) and Remote/TCP (for XMD) targets.
R Chapter 12: GNU Debugger At this point, mb-gdb is connected to XMD and controls the debugging. The simple but powerful GUI can be used to debug the program, read and write memory and registers. GDB Built-in Simulator The MicroBlaze debugger provides an instruction set simulator, which can be used to debug programs that do not access any peripherals.
R PowerPC Targets Note: The simulators provide a non-intrusive method of debugging a program. Debugging using the hardware target is intrusive because it needs an xmdstub to be running on the board. Note: If the program has any I/O functions like print() or putnum(), that write output onto the UART or JTAG Uart, it will be printed on the console/terminal where the xmd server was started. (Refer to the MicroBlaze Libraries documentation for libraries and I/O functions information).
R Chapter 12: GNU Debugger GDB Command Reference For help on using mb-gdb, click on Help o Help Topics in the GUI mode or type “help” in the console mode. In the GUI mode, to open a console window, click on View o Console For a comprehensive online documentation on using GDB, refer to the GNU website. For information about the mb-gdb Insight GUI, refer to the Red Hat Insight webpage http://sources.redhat.com/insight. Table 12-1 briefly describes the commonly used mb-gdb console commands.
R Chapter 13 Xilinx Microprocessor Debugger (XMD) The Xilinx Microprocessor Debugger (XMD) is a tool that facilitates a unified GDB interface as well as a Tcl (Tool Command Language) interface for debugging programs and verifying systems using the PowerPC (Virtex-II Pro & Virtex4) or MicroBlaze microprocessors.
R Chapter 13: Xilinx Microprocessor Debugger (XMD) GDB mb-gdb or PowerPC-eabi-gdb Tcl/Terminal Interface GDB Remote Protocol (TCP/IP) XMD PowerPC ISS PowerPC Hardware Board MicroBlaze Instruction Set Simulator MicroBlaze Hardware Board X10135 Figure 13-1: XMD Targets XMD Usage To start the XMD engine, execute xmd from a shell as follows. > xmd [xmd Tcl script] On startup, XMD does the following: 186 x If an xmd TCL script is specified, xmd will execute the script and quit.
R XMD Usage Table 13-1: XMD User Commands command [options] xload [mhs mhsfile] [mss mssfile] Description Load MHS/MSS system files. XMD reads MHS and MSS system files for the following reasons: x To infer the connectivity of FSL (Fast Synchronous Link) Bus between opb_mdm (MicroBlaze Debug Module) module and MicroBlaze. This connectivity is used to download program and data at a very fast rate. Fast Download on Microblaze in users guide describes fast download on MicroBlaze.
R Chapter 13: Xilinx Microprocessor Debugger (XMD) command [options] Description dow [-data] filename [addr] Download the given ELF or data file (with -data option) onto the current target’s memory. If no address is provided along with ELF file, the download address is determined from the ELF file by reading its headers.
R PowerPC Target In the case of xilinx_svffile, the JTAG commands are written into a file specified by the fname option x port Valid arguments for port are lpt1, lpt2 x fname Filename for creating the SVF file JTAG chain options x partname Name of the device x devicenr Position of the device in the JTAG chain x irlength Length of the IR register of the device.
R Chapter 13: Xilinx Microprocessor Debugger (XMD) x isocmsize Size of the ISBRAM memory connected to the ISOCM interface x isocmdcrstartadr DCR address corresponding to the ISOCM interface specified using the TIEISOCMDCRADDR signals on PowerPC x tlbstartadr Start address for reading and writing the Translation Look-aside Buffer x dcrstartadr Start address for reading and writing the Device Control Registers.
R PowerPC Target XMD JTAG JTAGPPC PPC 405 JTAG Signals PowerPC 405 X9988 Figure 13-2: PowerPC Target Example debug session with a PowerPC target This example demonstrates a simple debug session with a PowerPC target. Basic xmdbased commands are used after connecting to the PowerPC target using the “ppcconnect” command. At the end of the session, GDB (powerpc-eabi-gdb) is connected to xmd using the GDB remote target.
R Chapter 13: Xilinx Microprocessor Debugger (XMD) XMD: Connected to PowerPC target. Processor Version No : 0x20010820 PC: 0xffffef20 Address mapping for accessing special PowerPC features from XMD/GDB: I-Cache (Data) : Disabled I-Cache (Tag) : Disabled D-Cache (Data) : Disabled D-Cache (Tag) : Disabled ISOCM : Disabled TLB : Disabled DCR : Disabled Connected to PowerPC target.
R PowerPC Target FFFFC000: 00000000 FFFFC004: 00000000 FFFFC008: 00000000 FFFFC00C: 00000000 FFFFC010: 00000000 XMD% mwr 0xFFFFC004 0xabcd1234 2 XMD% mwr 0xFFFFC010 0xa5a50000 XMD% mrd 0xFFFFC000 5 FFFFC000: 00000000 FFFFC004: ABCD1234 FFFFC008: ABCD1234 FFFFC00C: 00000000 FFFFC010: A5A50000 XMD% XMD: Accepted a new GDB connection from nnn.nnn.n.
R Chapter 13: Xilinx Microprocessor Debugger (XMD) RUNNING> 8 Processor stopped at PC: 0xffffe218 XMD% bpl HW BP: BP_ID 0 : addr = 0xffffe218 <--- Automatic Hardware Breakpoint for ISOCM XMD% mrd 0xFFFFE218 Warning: Attempted to read location: 0xffffe218.
R PowerPC Simulator Target 2 0123e093 10 XC2VP4 XMD: Connected to PowerPC target. Processor Version No : 0x20010820 PC: 0xffffee18 Address mapping for accessing special PowerPC features from XMD/GDB: I-Cache (Data) : Disabled I-Cache (Tag) : Disabled D-Cache (Data) : Disabled D-Cache (Tag) : Disabled ISOCM : Disabled TLB : Disabled DCR : Disabled Connected to PowerPC target.
R Chapter 13: Xilinx Microprocessor Debugger (XMD) XMD TCP/IP Socket Connection PowerPC 405 Cycle_Accurate ISS ISS405.icf X10136 Figure 13-3: PowerPC ISS Target PowerPC Simulator target options When no option is specified to ppcconnect sim, xmd starts the ISS with default configuration and connects to ISS. Optionally an user can specify IP address, to connect to host running ISS.
R MicroBlaze MDM Target Starting GDB server for target (id = 0) at TCP port no 1234 XMD% dow dhry2.elf XMD% bps 0xffff09d0 XMD% traceopen trace.out XMD% tracestart XMD% con Processor started. Type "stop" to stop processor RUNNING> XMD% tracestop XMD% traceclose XMD% stats trace.
R Chapter 13: Xilinx Microprocessor Debugger (XMD) supports non-intrusive debugging using hardware breakpoints and hardware single-step, without the need for a ROM monitor like xmdstub.
R MicroBlaze MDM Target Valid arguments for port are lpt1, lpt2 x fname Filename for creating the SVF file JTAG chain options x partname Name of the device x devicenr Position of the device in the JTAG chain x irlength Length of the IR register of the device. This information can be found in the device BSDL file.
R Chapter 13: Xilinx Microprocessor Debugger (XMD) PARAMETER C_MB_DBG_PORTS = 1 PARAMETER C_USE_UART = 1 PARAMETER C_UART_WIDTH = 8 PARAMETER C_BASEADDR = 0x0000c000 PARAMETER C_HIGHADDR = 0x0000c0ff BUS_INTERFACE SOPB = mb_opb PORT OPB_Clk = sys_clk_s PORT DBG_CAPTURE_0 = DBG_CAPTURE_s PORT DBG_CLK_0 = DBG_CLK_s PORT DBG_REG_EN_0 = DBG_REG_EN_s PORT DBG_TDI_0 = DBG_TDI_s PORT DBG_TDO_0 = DBG_TDO_s PORT DBG_UPDATE_0 = DBG_UPDATE_s END 2.
R MicroBlaze MDM Target BEGIN fsl_v20 PARAMETER INSTANCE = download_link PARAMETER HW_VER = 1.00.b PARAMETER C_EXT_RESET_HIGH = 0 PORT SYS_Rst = sys_rst PORT FSL_Clk = sys_clk END XMD JTAG opb_mdm UART MDM MFSLO OPB Bus FSL Bus (Data to Download) MicroBlaze Debug Signals SFSLO MicroBlaze BRAM (or) External Memory BRAM X10137 Figure 13-5: MicroBlaze-MDM connection for Fast Download When the MHS file is loaded, xmd infers this connectivity automatically.
R Chapter 13: Xilinx Microprocessor Debugger (XMD) Note: Unlike the MicroBlaze stub target, programs should be compiled in executable mode and NOT in xmdstub mode while using the MDM target. Consequently, users need NOT specify a XMDSTUB_PERIPHERAL for compiling the xmdstub Example debug session with a MicroBlaze MDM target This example demonstrates a simple debug session with a MicroBlaze MDM target. Basic xmd-based commands are used after connecting to the MDM target using the “mbconnect” command.
R MicroBlaze MDM Target BREAKPOINT at 114: F1440003 sbi r10, r4, 3 XMD% dis 0x114 10 114: F1440003 sbi r10, r4, 3 118: E0E30004 lbui r7, r3, 4 11C: E1030005 lbui r8, r3, 5 120: F0E40004 sbi r7, r4, 4 124: F1040005 sbi r8, r4, 5 128: B800FFCC bri -52 12C: B6110000 rtsd r17, 0 130: 80000000 Or r0, r0, r0 134: B62E0000 rtid r14, 0 138: 80000000 Or r0, r0, r0 XMD% dow microblaze_0/code/executable.elf XMD% con Processor started.
R Chapter 13: Xilinx Microprocessor Debugger (XMD) Example debug session with 2 MicroBlaze processors and using the JTAG-based UART in MDM $ xmd Xilinx Microprocessor Debug (XMD) Engine Xilinx EDK 6.2 Build EDK_Gm.9 Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
R MicroBlaze MDM Target r6: 00000000 r14: 00000000 r7: 00000000 r15: 00000130 pc: 00000188 msr: 00000000 XMD% targets 0 Setting current target to target id 0 List of connected targets r22: 00000000 r23: 00000000 r30: 00000000 r31: 00000000 Target ID Target Type -----------------------------0 MicroBlaze MDM-based (hw) Target * 1 MicroBlaze MDM-based (hw) Target XMD% rrd r0: 00000000 r8: 00000000 r16: 00000000 r24: 00000000 r1: 00000548 r9: 0000006c r17: 00000000 r25: 00000000 r2: 00000190 r10: 0000006c
R Chapter 13: Xilinx Microprocessor Debugger (XMD) Note: The number of PC hardware breakpoints, setting and clearing the breakpoints are automatically managed by xmd when the “bps ” and “bpr ” commands are used. For address breakpoint (catchpoints), currently users have to explicitly set the breakpoint using the breakpoint ID and “xbreakpoint” command.
R MicroBlaze MDM Target r2: 000001e8 r10: 00000000 r18: 00000000 r3: 00000000 r11: 00000000 r19: 00000000 r4: 00000000 r12: 00000000 r20: 00000000 r5: 0000c000 r13: 000001e8 r21: 00000000 r6: 00000042 r14: 00000000 r22: 00000000 r7: 00000000 r15: 00000130 r23: 00000000 pc: 00000190 msr: 00000000 XMD% dis 0x188 5 188: E8650008 lwi r3, r5, 8 18C: A4630001 andi r3, r3, 1 190: BC03FFF8 beqi r3, -8 194: C8602800 lw r3, r0, r5 198: B60F0008 rtsd r15, 8 XMD% xbreak 0 0xC000 hw 4 Setting breakpoint at 0x0000c000
R Chapter 13: Xilinx Microprocessor Debugger (XMD) $ xmd Xilinx Microprocessor Debug (XMD) Engine Xilinx EDK 6.2 Build EDK_Gm.9 Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
R MicroBlaze Stub Target Serial Port options x -port Specify the serial port to which the remote hardware is connected, when xmd communication is over the serial cable. The default serial port is /dev/ttya on Solaris and Com1 on Windows x -baud Specify the serial port baud rate in bps. The default value is 19200 bps.
R Chapter 13: Xilinx Microprocessor Debugger (XMD) To debug a program by downloading on the remote hardware board, the program must be compiled with -g -xl-mode-xmdstub options to mb-gcc. Note: User Program outputs. If the program has any I/O functions like print() or putnum(), that write output onto the UART or JTAG Uart, it will be printed on the console/terminal where the xmd was started. (Refer to the MicroBlaze Libraries chapter for libraries and I/O functions information).
R MicroBlaze Simulator Target Platform Generator can create a system that includes a JTAG Uart or a Uart, if specified in the system’s mhs file. For more information on creating a system with a Uart or a JTAG Uart, refer to the MicroBlaze Hardware Specification Format chapter. The cables supported with the xmdstub mode are : Xilinx Parallel Cable III and Parallel Cable IV. x xmdstub on the board uses the JTAG Uart or Uart to communicate with the host computer.
R Chapter 13: Xilinx Microprocessor Debugger (XMD) Size of the memory address bus allocated in the simulator.
R XMD Internal Tcl Commands x xcontinue target [addr] Continue execution from the current PC or from the optional address argument. x xcycle_step target [cycles] Cycle step through one clock cycle of PowerPC ISS. If cycles is specified, then step “cycles” number of clock cycles. Note: This command is only for PowerPC ISS target. x xstep target Single step one MicroBlaze instruction. If the PC is at an IMM instruction the next instruction is executed as well.
R Chapter 13: Xilinx Microprocessor Debugger (XMD) x xstats target [options] Display the simulation statistics for the current session.’reset’ option can be provided to reset the simulation statistics. x xtargets [target] Print the target ID and target type of all current targets or a specific target. x xtraceopen target [filename] Open a trace file to collect trace information. If filename is not specified, isstrace.out is used as the default filename.
R Chapter 14 Platform Specification Format (PSF) The Platform Specification Format (PSF) defines the compatible set of infrastructure files for a EDK tool release. The infrastructure files are BBD, MDD, MHS, MPD, MSS, and PAO files.
R Chapter 14: Platform Specification Format (PSF) MSS - Microprocessor Software Specification An MSS file is supplied by the user as an input to the Library Generator (LibGen). The MSS file contains directives for customizing libraries, drivers and file systems. Please see Chapter 19, “Microprocessor Software Specification (MSS),” for more information.
R Load Path Format x _vX_Y_Z.mpd x _vX_Y_Z.bbd x _vX_Y_Z.pao x _vX_Y_Z.mdd Load Path Refer to Figure 14-1 for a depiction of the peripheral directory structure. To specify additional directories, use one of the following options: x Current directory x Set the EDK tool option -lp option EDK tools use a search priority mechanism to locate peripherals, as follows: 1. Search the pcores directory in the project directory 2.
R Chapter 14: Platform Specification Format (PSF) Is Your IP Pure HDL? Read about MPD and PAO files. The MPD keyword IPTYPE has the value HDL. Is Your IP Only A Black-Box Netlist? Read about MPD and BBD files. The MPD keyword IPTYPE has the value BLACKBOX. Is Your IP A Mixture Of Black-Box Netlists And VHDL or Verilog? Read about MPD, BBD, and PAO files. The MPD keyword IPTYPE has the value MIX. 218 www.xilinx.com 1-800-255-7778 Embedded System Tools Guide (EDK 6.2i) UG111 (v1.
R Chapter 15 Microprocessor Hardware Specification (MHS) The Microprocessor Hardware Specification (MHS) file defines the hardware component. An MHS file is supplied by the user as an input to the Platform Generator (PlatGen) tool.
R Chapter 15: Microprocessor Hardware Specification (MHS) However, Verilog allows such a declaration: microblaze microblaze ( ); It is also illegal in VHDL to declare an object (parameter/component/instance/signal) name that already exists as a name of another object. For example, it is illegal to declare in VHDL a signal name, MYTESTNAME, and also declare an instance name of MYTESTNAME. signal MYTESTNAME : std_logic; MYTESTNAME : microblaze port map ( ); However, this is legal in Verilog.
R MHS Syntax # Assign power signals PORT vcc_out = net_vcc, DIR=OUTPUT PORT gnd_out = net_gnd, DIR=OUT PORT gnd_out6 = net_gnd, DIR=OUTPUT, VEC=[0:5] PORT intr1 = intr_1, DIR=IN, SENSITIVITY=EDGE_RISING, SIGIS=INTERRUPT PORT intr2 = intr2, DIR=INPUT, SENSITIVITY=LEVEL_HIGH, SIGIS=INTERRUPT # Assign constant signals PORT const1 = 0b1010, DIR=OUTPUT, VEC=[0:3] PORT const2 = 0xC, DIR=OUTPUT, VEC=[0:3] PORT sys_rst = sys_rst, DIR=IN PORT sys_clk = sys_clk, DIR=IN, SIGIS=CLK PORT gpio_io = gpio_io, DIR=INOUT,
R Chapter 15: Microprocessor Hardware Specification (MHS) ###################################################################### BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = my_ilmb_cntlr1 PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00000fff BUS_INTERFACE SLMB = ilmb_v10 BUS_INTERFACE BRAM_PORT = ilmb1_porta END ###################################################################### BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = my_dlmb_cntlr1 PARAMETER HW_VER = 1.00.
R Global Parameter The following list are recommendations for bus labels: Table 15-1: Bus Labels Bus Name Description SDCR Slave DCR interface SLMB Slave LMB interface MOPB Master OPB interface MSOPB Master-slave OPB interface SOPB Slave OPB interface MPLB Master PLB interface MSPLB Master-slave PLB interface SPLB Slave PLB interface For components that have more than one bus interface, please look at the MPD file for a definition of listed bus interface labels.
R Chapter 15: Microprocessor Hardware Specification (MHS) Format PARAMETER VERSION = 2.1.0 The version is specified as a literal of the form 2.1.0. Local Parameter A local parameter is defined between a BEGIN-END block. A local parameter can have the following keywords: Table 15-3: Local Parameter Keywords Keyword Values Default 1.00.a No Default Hardware version No Default User-defined instance name.
R Global Port Format BUS_INTERFACE MOPB=opb_bus_inst, POSITION=integer Where integer is a positive integer. Highest position is "1". The order of assignment is retained as listed in the MHS in top-to-bottom order. Note: When specifying bus interfaces of master-slave like MSPLB or MSOPB, then there is a possibility that PlatGen will error out when you have more masters than slaves on the bus. The reason is the MSPLB or MSOPB is assigned a position.
R Chapter 15: Microprocessor Hardware Specification (MHS) EDGE The edge sensitivity of an interrupt signal is specified by the EDGE keyword. Its use is deprecated. Please use the SENSITIVITY keyword. Format PORT interrupt = "", DIR=O, EDGE=edge_value, SIGIS=INTERRUPT Where edge_value is either RISING or FALLING. LEVEL The level sensitivity of an interrupt signal is specified by the LEVEL keyword. Its use is deprecated. Please use the SENSITIVITY keyword.
R Local Port Where the value is either CLK, INTERRUPT, or RST.
R Chapter 15: Microprocessor Hardware Specification (MHS) The range specified by C_BASEADDR and C_HIGHADDR must comprise a complete, contiguous power-of-two range, such that range = 2N, and the N least significant bits of C_BASEADDR must be zero. Power Signals (net_gnd/net_vcc) Power signals are signals that are constantly driven with either GND (net_gnd) or VCC (net_vcc). Format PORT mysignal = power_signal In this example, power_signal is either “net_vcc” or “net_gnd”.
R Design Considerations Concatenation is done on A, B, C, and D connecting to port Y of [7:0]. This maps to the following: Y[7]=A, Y[6]=B[1], Y[5]=B[0], Y[4]=C, Y[3]=D[0], Y[2]=D[1], Y[1]=D[2], and Y[0]=D[3]. Concatenation is also useful for extending a vector’s length. Use 0b denotation to define a binary constant or 0x for a hex constant. An underscore (_) can be used for readability.
R 230 Chapter 15: Microprocessor Hardware Specification (MHS) www.xilinx.com 1-800-255-7778 Embedded System Tools Guide (EDK 6.2i) UG111 (v1.
R Chapter 16 Microprocessor Peripheral Description (MPD) The Microprocessor Peripheral Definition (MPD) file defines the interface of the peripheral.
R Chapter 16: Microprocessor Peripheral Description (MPD) Comments You can insert comments in the MPD file without disrupting processing. The following are guidelines for inserting comments: x Precede comments with the pound sign (#) x Comments continue to the end of the line x Comments can be anywhere on the line Format Use the following format at the beginning of a component definition: BEGIN peripheral_name The BEGIN keyword signifies the beginning of a new peripheral.
R Bus Interface BUS_INTERFACE BUS=SOPB, BUS_STD=OPB, BUS_TYPE=SLAVE ## Generics for VHDL or Parameters for Verilog PARAMETER C_BASEADDR=0xFFFFFFFF, DT=std_logic_vector, MIN_SIZE=0x100, BUS=SOPB PARAMETER C_HIGHADDR=0x00000000, DT = std_logic_vector, BUS=SOPB PARAMETER C_OPB_DWIDTH=32, DT=integer, BUS=SOPB PARAMETER C_OPB_AWIDTH=32, DT=integer, BUS=SOPB PARAMETER C_GPIO_WIDTH=32, DT=integer PARAMETER C_ALL_INPUTS=0, DT=integer ## Ports PORT OPB_Clk = “”, DIR=IN, SIGIS=CLK, BUS=SOPB PORT OPB_Rst = OPB_Rst,
R Chapter 16: Microprocessor Peripheral Description (MPD) Bus Interface Keywords A bus interface can have the following keywords: Table 16-1: Bus Interface Keywords Keyword Values Default Definition BUS string No Default Bus label BUS_STD DCR No Default Bus standard No Default Bus type FSL DSOCM ISOCM LMB OPB PLB TRANSPARENT BUS_TYPE MASTER MASTER_SLAVE SLAVE UNDEF EXCLUDE_BUSIF string No Default Name all BUS_INTERFACE connections that are not allowed when other BUS_INTERFACE connect
R Bus Interface Format BUS_INTERFACE BUS=bus_label, BUS_STD=bus_std, BUS_TYPE=bus_type Where bus_type is either MASTER, MASTER_SLAVE, SLAVE, or UNDEF. EXCLUDE_BUSIF The EXCLUDE_BUSIF keyword defines all BUS_INTERFACE connections when other BUS_INTERFACE connections are present. Supports a colon “:” separated list of elements. But, may also take a single element. For example, a master-slave interface and slave interface connections are not allowed when the other is present.
R Chapter 16: Microprocessor Peripheral Description (MPD) For the MSPLB bus interface, it is recommended to separate the master interface and slave interface as MPLB and SPLB, respectively. The reason is the MSPLB is assigned a position. This means the master interface and the slave interface must reside at the same position. If given as separate interfaces for MPLB and SPLB, then each interface can have its own position assignment.
R Option Option Keywords An option can have the following keywords: Table 16-4: Option Keywords Keyword Values Default Definition ADDR_SLICE integer No Default Address slice of BRAM controller ALERT string No Default Alert message ARCH_SUPPORT string ALL AWIDTH integer No Default Address width BUS_STD DCR No Default Define bus standard of BUS components List of supported FPGA architectures DSOCM FSL ISOCM LMB OPB PLB CORE_STATE ACTIVE ACTIVE Core state DEPRECATED DEVELOPMENT
R Table 16-4: Chapter 16: Microprocessor Peripheral Description (MPD) Option Keywords Keyword IPTYPE Values Default BRIDGE IP Definition Type of component BUS BUS_ARBITER IP PERIPHERAL PROCESSOR IS_COMPATIBLE_WITH string No Default Identify backwards compatibility of previous versions LONG_DESC string No Default Allows a long description of the core to be displayed by the GUI tools MAX_MASTERS integer No Default Define maximum number of masters MAX_SLAVES integer No Default Define m
R Option (double word) wide and thus has ADDR_SLICE=28. The OPB data bus is 32 bits (word) wide and thus has ADDR_SLICE=29. ALERT A message alert for the IP core is specified with the ALERT keyword. Format OPTION ALERT = “This belongs to Xilinx” ARCH_SUPPORT List of supported FPGA architectures. Valid values: all, spartan2, spartan2e, spartan3, virtex, virtexe, virtex2, virtex2p. Default is ALL. Supports a colon “:” separated list of elements. But, may also take a single element.
R Chapter 16: Microprocessor Peripheral Description (MPD) Table 16-5: CORE_STATE Values CORE_STATE DEVELOPMENT OBSOLETE Definition Core is in development and will be synthesized each time PlatGen is executed (no cache of synthesis results) Core is obsolete. EDK tools issue an error that this core is no longer valid. DESC Allows a short description of the core to be displayed by the GUI tools. The short description replaces the core name in display field of the core.
R Option The following table lists IP_GROUP values: Table 16-6: IP_GROUP Values IP_GROUP Definition ALLIANCE Third party IPs INFRASTRUCTURE All IPs in EDKInfrastructureLib LOGICORE All IPs in LogiCoreLib REFERENCE All IPs in XilinxReferenceDesigns USER User IPs (default) IPLEVEL_DRC_PROC The IPLEVEL_DRC_PROC keyword defines the Tcl entry point for the IP-level DRC routine. Do DRCs based only on IP-level settings. Currently, unsupported.
R Chapter 16: Microprocessor Peripheral Description (MPD) Format OPTION IS_COMPATIBLE_WITH = 1.00.a LONG_DESC Allows a long description of the core to be displayed by the GUI tools. The long description allows the GUI tools to display a hover help. No default. Format OPTION LONG_DESC = “OPB GPIO - IO only GPIO” MAX_MASTERS Define maximum number of masters allowed for cores marked as IPTYPE=BUS or IPTYPE=BUS_ARBITER. No default.
R Option Format OPTION SPECIAL = BRAM_CNTLR This keyword is reserved for internal use only. STYLE The STYLE keyword defines the design composition of the peripheral. If you have only optimized hardware netlists, you must specify the BLACKBOX value within the MPD file. In this case, only the BBD file is read by the EDK tools. If you have a mix of optimized hardware netlists and HDL files, you must specify the MIX value within the MPD file. In this case, the PAO and BBD files are read by the EDK tools.
R Chapter 16: Microprocessor Peripheral Description (MPD) The following table lists USAGE_LEVEL values: Table 16-9: USAGE_LEVEL Values USAGE_LEVEL ADVANCED_USER ALL_USERS Definition Core can not be configured by BSB Core can be configured by BSB (default) Parameter A parameter defines a constant that is passed into the entity (VHDL) or module (Verilog) declaration.
R Parameter Table 16-10: Parameter Keywords Keyword DT Values Default Definition integer No Default Datatype. See datatype translation table in the DT description for details. ALL_USERS Defines GUI usage level. Currently, unsupported. string std_logic std_logic_vector GUI_PERMIT ADVANCED_USER ALL_USERS DISPLAYONLY NONE IO_IF string No Default IO_IS string No Default IPLEVEL_UPDATE_PROC string No Default Tcl entry point for the IP-level update routine. Currently, unsupported.
R Chapter 16: Microprocessor Peripheral Description (MPD) ADDR_TYPE The ADDR_TYPE keyword identifies an address parameter of a defined memory class.
R Parameter BUS The bus interface of an parameter is specified by the BUS keyword. Format PARAMETER C_OPB_AWIDTH = 32, DT=datatype, BUS=bus_label Where bus_label is a string. If you have more than bus interface is sharing the parameter, then use the colon (:) to separate each bus interface in the list. The first item in the list is the default setting. CACHEABLE The CACHECABLE keyword identifies a cacheable address.
R Chapter 16: Microprocessor Peripheral Description (MPD) The following table lists GUI_PERMIT values: Table 16-15: GUI_PERMIT Values GUI_PERMIT ADVANCED_USER ALL_USERS Definition EDK GUI tools do not display EDK GUI tools ask user to set a value DISPLAYONLY EDK GUI tools display to user, however, does not allow user to modify or add to MHS NONE EDK GUI tools do not display to user.
R Port PAIR The PAIR keyword tags unidentified BASEADDR-HIGHADDR pairs. If non-standard names are used instead of C_BASEADDR and C_HIGHADDR, then address parameters must identify pairs that define the BASE and HIGH. Must use the ADDRESS keyword to identify parameter as BASE address or HIGH address. Format PARAMETER C_HIGH=0x00000000, PAIR=C_BASE, ADDRESS=HIGH PARAMETER C_BASE=0xFFFFFFFF, PAIR=C_HIGH, ADDRESS=BASE RANGE Defines a range of allowed valid values.
R Chapter 16: Microprocessor Peripheral Description (MPD) Port Keywords A port can have the following keywords: Table 16-16: Port Keywords Keyword 3STATE Values Default Definition TRUE No Default Tri-state expansion (deprecated) OPTIONAL Defines assignment usage level FALSE ASSIGNMENT CONSTANT OPTIONAL REQUIRE UPDATE BUS string No Default Bus label DESC string No Default Allow a short description of the port to be displayed by the GUI tools IN, INPUT, I O DIR Direction mode OUT, OU
R Port Table 16-16: Port Keywords Keyword LEVEL Values Default Definition HIGH No Default Interrupt level sensitivity (deprecated) LOW LONG_DESC string No Default Allow a long description of the port to be displayed by the GUI tools SENSITIVITY EDGE_FALLING No Default Interrupt sensitivity No Default Signal classification No Default Tri-state expansion No Default Vector dimension. Where A and B are positive integer expressions.
R Chapter 16: Microprocessor Peripheral Description (MPD) The following table lists ASSIGNMENT values: Table 16-17: ASSIGNMENT Values ASSIGNMENT Definition CONSTANT The value is a constant. User and the EDK batch tools are not allowed to modify the value.
R Port Where edge_value is either RISING or FALLING. ENABLE Tri-state signals can have multi-bit enable control, or a single bit enable control on the bus. This is specified with the ENABLE keyword. Format PORT mysignal = “”, DIR=IO, VEC=[0:31], ENABLE=enable_value Where enable_value is either SINGLE or MULTI. If there is no specification, then SINGLE is the default value. Please see the “Design Considerations” section about designing tri-state signals at the HDL level.
R Chapter 16: Microprocessor Peripheral Description (MPD) The level is dependent on the speed of the interface that the IP controls. For example, a UART runs at default 19200 baud, which gives a byte-rate of around 2000 bytes/s. An ethernet 100 runs at 100 MHz, which gives a byte-rate of 12 000 000 bytes/s. Therefore, UART is LOW and ethernet is HIGH. CANBus runs at 1 MHz and gives a byte-rate of 120 000 bytes/s which would be MEDIUM. It is also dependent if the IP has FIFO or not.
R Port LONG_DESC Allows a long description of the port to be displayed by the GUI tools. The long description allows the GUI tools to display a hover help. No default. Format PORT OPB_Clk="", DIR=I, SIGIS=CLK, BUS=SOPB, LONG_DESC="Clock from OPB" SENSITIVITY The interrupt sensitivity of an interrupt signal is specified by the SENSITIVITY keyword. This supersedes the EDGE and LEVEL keywords.
R Chapter 16: Microprocessor Peripheral Description (MPD) Format PORT PAR="", DIR=INOUT, THREE_STATE=FALSE, IOB_STATE=BUF For output ports, the default value is FALSE. For inout ports, the default value is TRUE. Please see the “3-state (InOut) Signals” section about designing tri-state signals at the HDL level. VEC The vector width of a signal is specified by the VEC keyword. Format PORT mysignal = “”, DIR=INPUT, VEC=[A:B] Where A and B are positive integer expressions.
R Port Where is a meaningful name or acronym for the slave output. An additional requirement on is that it must not contain the string, “DCR” (upper or lower case or mixed case), so that slave outputs will not be confused with bus outputs. uart_dcrAck intc_dcrAck memcon_dcrAck DCR Slave Inputs For interconnection to the DCR, all slaves must provide the following inputs: _ABus _Sl_DBus _Read _Write Where is a meaningful name or acronym for the slave input.
R Chapter 16: Microprocessor Peripheral Description (MPD) Master OPB Ports Naming conventions should be followed for that part of the identifier following the last underscore in the name. OPB Master Outputs For interconnection to the OPB, all masters must provide the following outputs: _ABus _BE _busLock _DBus _request _RNW _select _seqAddr Where is a meaningful name or acronym for the master output.
R Port Where is a meaningful name or acronym for the slave output. An additional requirement on is that it must not contain the string, “OPB” (upper or lower case or mixed case), so that slave outputs will not be confused with bus outputs.
R Chapter 16: Microprocessor Peripheral Description (MPD) PLB Master Inputs For interconnection to the PLB, all masters must provide the following inputs: _MAddrAck _MBusy _MErr _MRdBTerm _MRdDAck _MRdDBus _MRdWdAddr _MRearbitrate _MWrBTerm _MWrDAck _MSSize Where is a meaningful name or acronym for the master input.
R Reserved Parameter Names _PAValid _RNW _abort _busLock _compress _guarded _lockErr _masterID _MSize _ordered _pendPri _pendReq _reqPri _size _type _rdPrim _SAValid _wrPrim _wrBurst _wrDBus _rdBurst Where is a meaningful name or acronym for the slave input.
R Chapter 16: Microprocessor Peripheral Description (MPD) Table 16-20: Automatically Expanded Reserved Parameters Parameter Description C_DCR_NUM_SLAVES Number of DCR slaves C_LMB_AWIDTH LMB Address width C_LMB_DWIDTH LMB Data width C_LMB_MASK LMB Decode Mask C_LMB_NUM_SLAVES Number of LMB slaves C_OPB_AWIDTH OPB Address width C_OPB_DWIDTH OPB Data width C_OPB_NUM_MASTERS Number of OPB masters C_OPB_NUM_SLAVES Number of OPB slaves C_PLB_AWIDTH PLB Address width C_PLB_DWIDTH PLB Data
R Reserved Parameter Names Where is a hex value. C_NUM_MASTERS The C_NUM_MASTERS parameter defines the number of OPB masters on the bus. This parameter is automatically populated by the EDK tools. It’s use is deprecated. Please use the C_NUM_OPB_MASTERS parameter. Format PARAMETER C_NUM_MASTERS = , DT=integer Where is an integer value. C_NUM_SLAVES The C_NUM_SLAVES parameter defines the number of OPB slaves on the bus. This parameter is automatically populated by the EDK tools.
R Chapter 16: Microprocessor Peripheral Description (MPD) C_LMB_AWIDTH The C_LMB_AWIDTH parameter defines the LMB address width in bits. This parameter is automatically populated by the EDK tools. Format PARAMETER C_LMB_AWIDTH = , DT=integer Where is an integer value. C_LMB_DWIDTH The C_LMB_DWIDTH parameter defines the LMB data width in bits. This parameter is automatically populated by the EDK tools. Format PARAMETER C_LMB_DWIDTH = , DT=integer Where is an integer value.
R Reserved Parameter Names C_OPB_DWIDTH The C_OPB_DWIDTH parameter defines the OPB data width in bits. This parameter is automatically populated by the EDK tools. Format PARAMETER C_OPB_DWIDTH = , DT=integer Where is an integer value. C_OPB_NUM_MASTERS The C_OPB_NUM_MASTERS parameter defines the number of OPB masters on the bus. This parameter is automatically populated by the EDK tools. Format PARAMETER C_OPB_NUM_MASTERS = , DT=integer Where is an integer value.
R Chapter 16: Microprocessor Peripheral Description (MPD) C_PLB_MID_WIDTH The C_PLB_MID_WIDTH parameter defines the PLB master ID width in bits. This is determined by the number of PLB masters as shown in the following table: Table 16-21: C_PLB_MID_WIDTH Calculation C_PLB_NUM_MASTERS (Number of PLB Masters) C_PLB_MID_WIDTH 0 to 2 1 3 to 4 2 5 to 8 3 9 to 16 4 This parameter is automatically populated by the EDK tools.
R Reserved Port Connections LMB - Clock and Reset PORT LMB_Clk = “”, DIR=I, SIGIS=CLK PORT LMB_Rst = LMB_Rst, DIR=I OPB - Clock and Reset PORT OPB_Clk = “”, DIR=I, SIGIS=CLK PORT OPB_Rst = OPB_Rst, DIR=I PLB - Clock and Reset PORT PLB_Clk = “”, DIR=I, SIGIS=CLK PORT PLB_Rst = PLB_Rst, DIR=I Notice that the clock port has no default value. The clock port is an input to the bus and is assigned by the user in the MHS. Therefore, all peripherals on the bus must also be treated as a user input port.
R Chapter 16: Microprocessor Peripheral Description (MPD) PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT _busLock = M_busLock, DIR=O, BUS=MOPB _DBus = M_DBus, DIR=O, VEC=[0:C_OPB_DWIDTH-1], BUS=MOPB _request = M_request, DIR=O, BUS=MOPB _RNW = M_RNW, DIR=O, BUS=MOPB _select = M_select, DIR=O, BUS=MOPB _seqAddr = M_seqAddr, DIR=O, BUS=MOPB _DBus = OPB_DBus, DIR=I, VEC=[0:C_OPB_DWIDTH-1], BUS=MOPB _errAck = OPB_errAck, DIR=I, BUS=MOPB _MGrant = OPB_MGr
R Design Considerations PORT PORT PORT PORT _MRearbitrate = PLB_MRearbitrate, DIR=I, BUS=MPLB _MWrBTerm = PLB_MWrBTerm, DIR=I, BUS=MPLB _MWrDAck = PLB_MWrDAck, DIR=I, BUS=MPLB _MSSize = PLB_MSSize, DIR=I, VEC=[0:1], BUS=MPLB Slave PLB Ports For interconnection to the PLB, all slaves must provide the following connections: PORT _addrAck = Sl_addrAck, DIR=O, BUS=SPLB PORT _MErr = Sl_MErr, DIR=O, VEC=[0:C_NUM_MASTERS-1], BUS=SPLB PORT _MBusy = Sl_MBusy, DIR=O, VEC=[0:
R Chapter 16: Microprocessor Peripheral Description (MPD) An unconnected port is identified as an empty double-quote (““) string. The EDK tools resolves the driver value on unconnected input ports by the INITIALVAL keyword. Format PORT mysignal = “”, DIR=OUTPUT Scalable Data path Using an MPD keyword declaration, you can automatically scale data path width. Bus expressions are evaluated as arithmetic equations.
R Design Considerations 3-state (InOut) Signals At the MHS/MPD level, there is a listing for an inout port in the MPD file that allows you to map to it in the MHS file. In the MPD file, a 3-state signal is identified by the inout direction mode, and the port name must be ioname.
R Chapter 16: Microprocessor Peripheral Description (MPD) generic (C_WIDTH: integer:= 9); port ( -- tri-state signal tristate_I: in std_logic_vector(0 to C_WIDTH-1); tristate_O: out std_logic_vector(0 to C_WIDTH-1); tristate_T: out std_logic); end entity tri_state_single; MPD 3-state (InOut) With Single-Bit Enable Example The following is a MPD example that includes 3-state signal with a single-bit enable: BEGIN tri_state_single OPTION IPTYPE=IP PARAMETER C_WIDTH = 9, DT=integer PORT tristate = “”, DIR=I
R Chapter 17 Peripheral Analyze Order (PAO) A PAO (Peripheral Analyze Order) file contains a list of HDL files that are needed for synthesis, and defines the analyze order for compilation. The STYLE option in the MPD with the values of MIX or HDL identify the core as having a PAO file.
R 274 Chapter 17: Peripheral Analyze Order (PAO) www.xilinx.com 1-800-255-7778 Embedded System Tools Guide (EDK 6.2i) UG111 (v1.
R Chapter 18 Black-Box Definition (BBD) The Black Box Definition (BBD) file manages the file locations of optimized hardware netlists for the black-box sections of your peripheral design. The STYLE option in the MPD with the values of MIX or BLACKBOX identify the core as having a BBD file. This chapter contains the following sections. x “BBD Format” x “BBD Examples” BBD Format The BBD format is a look-up table chart that lists netlist files. The first line is the header of the look-up table.
R Chapter 18: Black-Box Definition (BBD) Lists If you have multiple hardware implementation netlists, then use a comma (,) to separate each individual netlist in the list. BBD Examples File Selection Without Options The following is an example of a file selection without options. The NGC netlist is copied into the your implementation directory regardless of specific options set on the core. FILES blackbox.
R Chapter 19 Microprocessor Software Specification (MSS) This chapter describes the Microprocessor Software Specification (MSS) format. The chapter contains the following sections. x “Overview” x “MSS Format” x “Global Parameters” x “Instance Specific Parameters” Overview An MSS file is supplied by the user as an input to the Library Generator (Libgen). The MSS file contains directives for customizing operating systems (OS), libraries, and drivers.
R Chapter 19: Microprocessor Software Specification (MSS) Parameter The MSS file has a simple name = value format for most statements. The parameter keyword is required before every such NAME, VALUE pairs. The format for assigning a value to a parameter is parameter name = value. If the parameter is within a begin-end block, it is a local assignment, otherwise it is a global (system level) assignment. Requirements The MSS file has a dependency on the MHS file.
R Global Parameters BEGIN PROCESSOR parameter HW_INSTANCE = my_ppc parameter DRIVER_NAME = cpu_ppc405 parameter DRIVER_VER = 1.00.a END BEGIN DRIVER parameter HW_INSTANCE = my_intc parameter DRIVER_NAME = intc parameter DRIVER_VER = 1.00.a END BEGIN DRIVER parameter HW_INSTANCE = my_uartlite_1 parameter DRIVER_VER = 1.00.a parameter DRIVER_NAME = uartlite parameter INT_HANDLER = uart_1_handler, INT_PORT = Interrupt END BEGIN DRIVER parameter HW_INSTANCE = my_uartlite_2 parameter DRIVER_VER = 1.00.
R Chapter 19: Microprocessor Software Specification (MSS) PSF Version This option specifies the PSF version of the MSS file. This option is mandatory for versions 2.1.0 and above. Format parameter VERSION = 2.1.0 Parameter INT_HANDLER This option defines the interrupt handler software routine for an external interrupt port given in the MHS file.
R Instance Specific Parameters PROC_INSTANCE Option This option is required for OS associated with a processor instances specified in the MHS file. Format parameter PROC_INSTANCE = instance_name All OS’es in the EDK require processor instances to be associated with the OS’es. The instance name that is given must match the name specified in the MHS file. HW_INSTANCE Option This option is required for drivers associated with peripheral instances specified in the MHS file.
R Chapter 19: Microprocessor Software Specification (MSS) Format parameter DRIVER_NAME = uartlite Library Generator copies the driver directory specified to OUTPUT_DIR/processor_instance_name/libsrc directory and compiles the drivers using makefiles provided. Please see the Chapter 7, “Library Generator” for more information. DRIVER_VER Option The driver version is set using the DRIVER_VER option. Format parameter DRIVER_VER = 1.00.a This version is specified in the following format: x.yz.
R Instance Specific Parameters This version is specified in the following format: x.yz.a, where x,y and z are digits, and a is a character. This is translated to the library directory searched by LibGen as follows: USER_PROJECT/sw_services/LIBRARY_NAME_vx_yz_a XILINX_EDK/sw/lib/sw_services/LIBRARY_NAME_vx_yz_a The MLD (Microprocessor Library Definition) files needed by Libgen for each library should be named LIBRARY_NAME_v_2_1_0.
R Chapter 19: Microprocessor Software Specification (MSS) parameter STDIN = my_uartlite_1 parameter STDOUT = my_uartlite_1 END Processor Specific Parameters Table 19-3: Parameters Specified in Processor Blocks Only Option Values Default Definition XMDSTUB_PER IPHERAL Instance name None Peripheral instance used for On-board Debug.
R Instance Specific Parameters part of the microblaze instance or powerpc instance. Any other compatible archiver can be specified as an option. Format parameter ARCHIVER = ar This denotes the archiver ar to be used for drivers and libraries. COMPILER_FLAGS Option This option specifies compiler flags to be used for compiling drivers and libraries. If the option is not specified, Libgen automatically uses platform and processor specific options.
R 286 Chapter 19: Microprocessor Software Specification (MSS) www.xilinx.com 1-800-255-7778 Embedded System Tools Guide (EDK 6.2i) UG111 (v1.
R Chapter 20 Microprocessor Library Definition (MLD) This chapter describes the Microprocessor Library Definition(MLD) format, Platform Specification Format 2.1.0. The chapter contains the following sections.
R Chapter 20: Microprocessor Library Definition (MLD) x Data Definition file - The MLD file (named as _v2_1_0.mld or _v2_1_0.mld) contains the configurable parameters . A detailed description of the various parameters and the MLD format is described in section“MLD Parameter Description Section” in this chapter. x Data Generation file - The second file (named as _v2_1_0.tcl or _v2_1_0.
R Example Example This section explains the MLD format through an example MLD file and its corresponding Tcl file. Example MLD file for a library An example MLD file for the xilmfs library is given below: OPTION psf_version = 2.1.0 ; OPTION is a keyword identified by the libgen tool. The option name following the OPTION keyword is a directive to the libgen tool to do a specific action. Here psf_version of the MLD file is defined to be 2.1.
R Chapter 20: Microprocessor Library Definition (MLD) PROPERTY defines the properties associated with the construct defined in the BEGIN construct. Here “HEADER” is a property with value “xilmfs.h”, defined by the “file” interface. FUNCTION defines a function supported by the interface. Here “open”, “close”, “read”, “write”, “lseek” are functions of “file” interface with values “mfs_file_open”, “mfs_file_close”, “mfs_file_read”, “mfs_file_write”, “mfs_file_lseek”.
R Example Example MLD file for an OS An example MLD file for the standalone OS is given below: OPTION psf_version = 2.1.0 ; OPTION is a keyword identified by the libgen tool. The option name following the OPTION keyword is a directive to the libgen tool to do a specific action. Here psf_version of the MLD file is defined to be 2.1. This is the only option that can occur before a BEGIN OS construct now. BEGIN OS standalone The BEGIN OS construct defines the start of an OS named “standalone”.
R Chapter 20: Microprocessor Library Definition (MLD) } "ppc405" { foreach entry [glob -nocomplain [file join $ppcsrcdir *]] { file copy -force $entry "./src/" } } "default" {puts "unknown processor type\n"} } # Remove microblaze and ppc405 directories...
R MLD Parameter Description Section [OPTION help = ] [OPTION requires_interface = ] PARAM [BEGIN CATEGORY END CATEGORY] BEGIN INTERFACE ....... END INTERFACE] END LIBRARY/OS Keywords The keywords that are used in an MLD/MDD file are as follows: begin The begin keyword begins one of the following - os, library, drive, block, category, interface, array.
R Chapter 20: Microprocessor Library Definition (MLD) Specifies the interfaces implemented by this os/library/driver. It describes the interface functions and header files used by the library/driver.
R Design Rule Check (DRC) Section int - integer string - string value within " " enum - list of possible values, that this parameter can take library - specify other library that is needed for building the library/driver. peripheral_instance - specify other hardware drivers that is needed for building the library. default: Specifies the default value for the entity in which it was defined. permit: Specifies the permissions for modification of values.
R Chapter 20: Microprocessor Library Definition (MLD) For Warnings, drc procedures return a string value which can be printed on the console. On Success, drc procedures just return without any value. Library Generation (Generate) Section proc mygenerate { handle } { } generate could be any Tcl code which reads the user parameters and generates configuration files for the os/library. The configuration files can be C files, Header files, Makefiles, etc.
R Chapter 21 Microprocessor Driver Definition (MDD) This chapter describes the Microprocessor Driver Definition (MDD) format, Platform Specification Format 2.1.0. The chapter contains the following sections. x “Overview” x “Requirements” x “Driver Definition Files” x “MDD Format Specification” x “Example” x “MDD Parameter Description” x “Design Rule Check (DRC) Section” x “Driver Generation Section (Generate)” Overview An MDD file contains directives for customizing software drivers.
R Chapter 21: Microprocessor Driver Definition (MDD) x Data Definition file - The MDD file (named as _v2_1_0.mdd) contains the configurable parameters . A detailed description of the various parameters and the MDD format is described in section“MDD Parameter Description,” in this chapter. x Data Generation file - The second file (named as _v2_1_0.
R Example MDD file example An example MDD file for the uartlite driver is given below: OPTION psf_version = 2.1; OPTION is a keyword identified by the libgen tool. The option name following the OPTION keyword is a directive to the libgen tool to do a specific action. Here psf_version of the MDD file is defined to be 2.1. This is the only option that can occur before a BEGIN DRIVER construct now. BEGIN DRIVER uartlite The BEGIN DRIVER construct defines the start of a driver named “uartlite”.
R Chapter 21: Microprocessor Driver Definition (MDD) function of “stdin” interface has a value “XUartLite_RecvByte”.This function is defined in the header file “xuartlite_l.h”. BEGIN INTERFACE stdout PROPERTY header = xuartlite_l.h; FUNCTION name = outbyte, value = XUartLite_SendByte; END INTERFACE BEGIN INTERFACE stdio PROPERTY header = xuartlite_l.
R MDD Parameter Description libgen for uartlite driver while running DRCs for drivers. The generate routine generates constants in a header file and a c file for uartlite driver based on the driver definition segment in the MSS file. proc uartlite_drc {drv_handle} { puts “UartLite DRC” } proc generate {drv_handle} { set level [xget_value $drv_handle "PARAMETER" "level"] if {$level == 0} { xdefine_include_file $drv_handle "xparameters.
R Chapter 21: Microprocessor Driver Definition (MDD) [BEGIN INTERFACE ....... END INTERFACE] END DRIVER Keywords The keywords that are used in an MLD/MDD file are as follows: begin The begin keyword begins one of the following - library, drive, block, category, interface, array. end The end keyword signifies the end of a definition block. psf_version: Specifies the psf version of the library. drc: Specifies the DRC function name.
R MDD Parameter Description BEGIN INTERFACE OPTION DEP=; PROPERTY HEADER=; FUNCTION NAME=, VALUE= ; END INTERFACE header: Specifies the header file in which the interface functions would be defined. function: Specifies the function implemented by the interface.
R Chapter 21: Microprocessor Driver Definition (MDD) If permit = none, then the category is always active. This property is still experimental. Tools do not perform any action for this property for EDK6.1 release.
R Driver Generation Section (Generate) can also get any other parameter from the database, by first requesting for a handle and using the handle to get the parameter Embedded System Tools Guide (EDK 6.2i) UG111 (v1.4) January 30, 2004 www.xilinx.
R 306 Chapter 21: Microprocessor Driver Definition (MDD) www.xilinx.com 1-800-255-7778 Embedded System Tools Guide (EDK 6.2i) UG111 (v1.
R Chapter 22 Address Management This chapter describes the embedded processor program address management techniques. For advanced address space management, a discussion on linker scripts is also included in this chapter.
R Chapter 22: Address Management memory region only. The total amount of on-chip memory available to a MicroBlaze system may exceed these limits. The total amount of memory available in the form of BRAMs is also FPGA device specific. Smaller devices of a given device family provide less BRAM than larger devices in the same device family.
R MicroBlaze Processor Memory Speeds and Latencies MicroBlaze requires 2 clock cycles to access on-chip Block RAM connected to the LMB for write and 2 clock cycles for read. On chip memory connected to the OPB bus requires 3 cycles for write and 4 cycles for read. External memory access is further limited by off-chip memory access delays for read access, resulting in 5-7 clock cycles for read. Furthermore, memory accesses over the OPB bus may incur further latencies due to bus arbitration overheads.
R Chapter 22: Address Management System with only an executable [No debug, No Bootstrap] The scenario is depicted in Figure 22-2(a). The C-runtime file crt0.o is linked with the user program. The system file, crt0.o starts at address location 0x0, immediately followed by user’s program. System with debugging support With systems requiring debug support, xmdstub must be downloaded at address location 0x0. The C-runtime file crt1.o is bundled with the user program and is place at a default location.
R MicroBlaze Processor Different Base Address, Non-contiguous User Address Space The users can place different components of their program on different memories. For example, on MicroBlaze systems with non-contiguous LMB and OPB memories, users can keep their code on LMB memory and the data on OPB memory. The users can also create systems which have contiguous address space for LMB and OPB memory, but having holes in the OPB address space.
R Chapter 22: Address Management section is accessed using absolute addresses. This section has the w (read-write) and the i (initialized) flags. Sectional Layout of an object or an Executable File .text Text Section .rodata Read-Only Data Section .sdata2 Small Read-Only Data Section .data Read-Write Data Section .sdata Small Read-Write Data Section .sbss Small Uninitialized Data Section .
R MicroBlaze Processor Note that using the built-in linker script implies that you have no control over which parts of your program are mapped to the different kinds of memory. The default scripts used by the linker are located at: $XILINX_EDK/gnu/microblaze/nt(orsol)/microblaze/lib/ldscripts, where $XILINX_EDK is the EDK installed directory. These scripts are imbibed into the linker and hence any changes to these scripts will not be reflected.
R Chapter 22: Address Management External Memory, and you may want to keep that portion of your code that is accessed the most frequently in LMB memory, and that which is accessed the least frequently in External Memory. You will need to provide a linker script to mb-gcc using the following command: mb-gcc -Wl,-T -Wl,linker_script file1.c file2.c -save-temps This tells mb-gcc to use your linker script only, and to not use the default (built-in) linker script.
R MicroBlaze Processor . += _STACK_SIZE; . = ALIGN(4); } >LMB _stack = .; /* */ /* Start of OPB memory */ /* */ .opb_text : { /* Uncomment the following line to add an executable section into */ /* opb memory */ /* file1.o(.text) */ } >OPB . = ALIGN(4); .rodata : { *(.rodata) } >OPB /* Alignments by 8 to ensure that _SDA2_BASE_ on a word boundary */ . = ALIGN(8); _ssrw = .; .sdata2 : { *(.sdata2) } >OPB . = ALIGN(8); _essrw = .; _ssrw_size = _essrw - _ssrw; _SDA2_BASE_ = _ssrw + (_ssrw_size / 2 ); .
R Chapter 22: Address Management . = ALIGN(4); __bss_end = .; } > OPB _end = .; } Note that if you choose to write a linker script, you must do the following to ensure that your program will work correctly. The example linker script given above incorporates these restrictions. Each of the restriction is highlighted in the example linker script. x Allocate space in the .bss section for stack and heap. Set the _heap variable to the beginning of this area, and the _stack variable to the end of this area.
R PowerPC Processor Figure 22-4 shows a sample address map for a PowerPC based EDK system. The figure shows that there can be various memories in the system. Here users need advanced address space management, which can be done with the help of linker script, described in the “Linker Script” section. Current Address Space Restrictions Special Addresses Every PowerPC system should have the boot section starting at 0xFFFFFFFC.
R Chapter 22: Address Management Advanced User Address Space Different Base Address, Contiguous User Address Space The user program can run from any memory. By default, the compiler places the user program at location 0xFFFF0000. To execute the program from any address location other than the default, users must provide the compiler powerpc-eabi-gcc with additional option.
R PowerPC Processor $XILINX_EDK/gnu/powerpc-eabi/nt(or sol)/powerpceabi/lib/ldscripts, where $XILINX_EDK is the EDK installed directory. These scripts are imbibed into the linker and hence any changes to these scripts will not be reflected. The choice of the default script that will be used by the linker from the $XILINX_EDK/gnu/powerpc-eabi/nt(orsol)/powerpc-eabi/lib/ldscripts area are described as below: x elf32ppc.x is used by default when none of the following cases apply x elf32ppc.
R Chapter 22: Address Management x Ensure that boot.o is the first file to be linked (Check the STARTUP(boot.o) in the following script which achieves this) x Ensure that the .vectors section is aligned on a 64k boundary. In order to ensure this, make .vectors as the first section defintion in the linker script. The memory where .vectors will be assigned to should start on a 64k boundary. Include this section definition only when your program uses interrupts/exceptions.
R PowerPC Processor */ SECTIONS { /* * .vectors section must be aligned on a 64k boundary * Hence should be the first section definition as bram start location is 64k aligned */ .vectors : { *(.vectors) } > bram .boot0 : { *(.boot0)} > bram .text : { *(.text) } > bram .boot : { *(.boot) } > boot .data : { *(.data) *(.got2) *(.rodata) *(.fixup) } > bram /* small data area (read/write): keep together! */ .sdata : { *(.sdata) } > bram .sbss : { . = ALIGN(4); *(.sbss) .
R Chapter 22: Address Management . = . + STACKSIZE; . = ALIGN(16); __stack = .; _heap_start = .; . = . + _HEAP_SIZE; . = ALIGN(16); _heap_end = .; } > bram __bss_start = ADDR(.bss); } 322 www.xilinx.com 1-800-255-7778 Embedded System Tools Guide (EDK 6.2i) UG111 (v1.
R Chapter 23 Interrupt Management This chapter outlines interrupt management in both MicroBlaze and PowerPC. It details the interrupt handling in MicroBlaze and PowerPC, and the role of LibGen for MicroBlaze and PowerPC. The chapter contains the following sections: x “Interrupt Management” x “MicroBlaze Interrupt Management” x “PowerPC Interrupt Management” x “Libgen Customization” x “Example Systems” x “Example Systems for PowerPC” Interrupt Management Prior to EDK 6.
R Chapter 23: Interrupt Management interrupt MicroBlaze Interrupt Source Figure 23-1: MicroBlaze connected to an Interrupt Source Figure 23-1 shows MicroBlaze connected to an interrupt source. The interrupt port is connected to the interrupt port of MicroBlaze. On interrupts, MicroBlaze jumps to address location 0x8. This is part of the C Runtime library and contains a jump to the default interrupt handler (_interrupt_handler).
R MicroBlaze Interrupt Management peripheral interrupt signals with priorities 1 through 4 connected to the interrupt controller input.
R Chapter 23: Interrupt Management store these routines corresponding to each of the interrupt signal. If an interrupt is active, the interrupt controller handler calls the routine correponding to it. An argument can be associated with such routines which gets passed when calling the routine. The vector table used by the interrupt controller handler is automatically generated by libgen.
R MicroBlaze Interrupt Management bus_interface DLMB = d_lmb bus_interface ILMB = i_lmb port INTERRUPT = interrupt end On interrupts, MicrBlaze jumps to thehandler of the timer peripheral using the exception table as defined in the “MicroBlaze Interrupt Management” section. If the timer peripheral’s handler is specified in the MSS file, this routine is automatically registered in the exception table by libgen.
R Chapter 23: Interrupt Management Interrupt Handlers Users are expected to write their own interrupt handlers (or Interrupt Service Routines) for any peripherals that raise interrupts. These routines can be written in C just like any other function. The interrupt handler function can have any name with the signature void func (void *). Interrupt Routines in MicroBlaze The following are the interrupts related routines defined in the MicroBlaze Board Support Package (BSP).
R Libgen Customization On interrupts, PowerPC jumps to the handler registered in the exception table. The user is required to register the handler of the interrupt source with the PowerPC exception table using a function(XExc_RegisterHandler) in the PowerPC Board Support Package (BSP). This function is provided by Xilinx. The Interrupt Source connected to PowerPC could be any of the following : x “Interrupt Controller Peripheral.” x “Peripheral with an Interrupt port.” x “External Interrupt Port.
R Chapter 23: Interrupt Management The interrupt controller driver uses the priorities and the maximum number of interrupt sources in a system as #defines. Libgen generates priorities for each of the interrupt signals as #defines in xparameters.
R Example Systems i On interrupts MicroBlaze jumps to the handler function using the exception table. Example MHS File Snippet BEGIN opb_timer parameter INSTANCE = mytimer parameter HW_VER = 1.00.b parameter C_BASEADDR = 0xFFFF0000 parameter C_HIGHADDR = 0xFFFF00ff bus_interface SOPB = opb_bus port Interrupt = interrupt port CaptureTrig0 = net_gnd END begin microblaze parameter INSTANCE = mblaze parameter HW_VER = 1.00.
R Chapter 23: Interrupt Management if ((count <<= 1) > 8) { count = 1; } /* Write value to gpio.
R Example Systems end Example MSS File snippet PARAMETER int_handler = global_int_handler, int_port = interrupt_in1 Example C Program #include
R Chapter 23: Interrupt Management ASK and XPAR_INTC_INSTANCE_NAME_INTERRUPT_SIGNAL_INTR. This can be used to enable or disable interrupts. 2. The interrupt handler functions for each interruptible peripheral must be written. 3. Each handler function is then designated to be the handler for an interrupt signal using the INT_HANDLER keyword in the MSS file. Alternately, the routines can be registered with the exception table in the user code.
R Example Systems parameter C_HIGHADDR = 0xFFFF10ff bus_interface SOPB = opb_bus port Irq = interrupt port Intr = timer1 & uart1 END begin microblaze parameter INSTANCE = mblaze parameter HW_VER = 1.00.c bus_interface DOPB = opb_bus bus_interface DLMB = d_lmb bus_interface ILMB = i_lmb port INTERRUPT = interrupt end Example MSS File snippet BEGIN DRIVER parameter HW_INSTANCE = mytimer parameter DRIVER_NAME = tmrctr parameter DRIVER_VER = 1.00.
R Chapter 23: Interrupt Management /* Set timer with new value of timer_count */ XTmrCtr_mSetLoadReg(XPAR_MYTIMER_BASEADDR, 0, (timer_count*tim er_count+1) * 1000000); } } } /* timer interrupt service routine */ void timer_int_handler(void * baseaddr_p) { unsigned int csr; unsigned int gpio_data; /* Read timer 0 CSR to see if it raised the interrupt */ csr = XTmrCtr_mGetControlStatusReg(XPAR_MYTIMER_BASEADDR, 0); if (csr & XTC_CSR_INT_OCCURED_MASK) { /* Increment the count */ if ((count <<= 1) > 8) { cou
R Example Systems for PowerPC XTmrCtr_mSetLoadReg(XPAR_MYTIMER_BASEADDR, 0, (timer_count*timer_count+1) * 1000000); /* reset the timers, and clear interrupts */ XTmrCtr_mSetControlStatusReg(XPAR_MYTIMER_BASEADDR, 0, XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK ); /* Enable timer and uart interrupts in the interrupt controller */ XIntc_mEnableIntr(XPAR_MYINTC_BASEADDR, XPAR_MYTIMER_INTERRUPT_MASK); /* start the timers */ XTmrCtr_mSetControlStatusReg(XPAR_MYTIMER_BASEADDR, 0, XTC_CSR_ENABLE_TMR_MASK | XTC_C
R Chapter 23: Interrupt Management 4. Libgen and powerpc-eabi-gcc are executed. Example MHS File Snippet BEGIN opb_timer parameter INSTANCE = mytimer parameter HW_VER = 1.00.b parameter C_BASEADDR = 0xFFFF0000 parameter C_HIGHADDR = 0xFFFF00ff bus_interface SOPB = opb_bus port Interrupt = interrupt port CaptureTrig0 = net_gnd END BEGIN ppc405 PARAMETER INSTANCE = PPC405_i PARAMETER HW_VER = 1.00.
R Example Systems for PowerPC Example C Program #include #include #include /* Global variables: count is the count displayed using the * LEDs, and timer_count is the interrupt frequency.
R Chapter 23: Interrupt Management /* reset the timers, and clear interrupts */ XTmrCtr_mSetControlStatusReg(XPAR_MYTIMER_BASEADDR, 0, XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK ); /* start the timers */ XTmrCtr_mSetControlStatusReg(XPAR_MYTIMER_BASEADDR, 0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK); /* Wait for interrupts to occur */ while (1) ; } Example MHS File Snippet (for external interrupt signal) PORT interrupt_in1 = interrupt_in1, D
R Example Systems for PowerPC Example C Program #include
R Chapter 23: Interrupt Management 3. Each handler function is then designated to be the handler for an interrupt signal using the INT_HANDLER keyword in the MSS file. Alternately, the routines can be registered with the exception table in the user code. For this example, we showcase both these usecases by setting the routine for timer in the MSS file and setting up the uart interrupt port handler in the user code. Note that intc interrupt signal must not be given an INT_HANDLER keyword.
R Example Systems for PowerPC PARAMETER HW_VER = 1.00.
R Chapter 23: Interrupt Management unsigned int count = 1; /* default count */ unsigned int timer_count = 1; /* default timer_count */ /* uartlite interrupt service routine */ void uart_int_handler(void *baseaddr_p) { char c; /* till uart FIFOs are empty */ while (!XUartLite_mIsReceiveEmpty(XPAR_MYUART_BASEADDR)) { /* read a character */ c = XUartLite_RecvByte(XPAR_MYUART_BASEADDR); /* if the character is between "0" and "9" */ if ((c>47) && (c<58)) { timer_count = c-48; /* print character on hypertermina
R Example Systems for PowerPC XExc_RegisterHandler(XEXC_ID_NON_CRITICAL_INT, (XExceptionHandler)XIntc_DeviceInterruptHandler, (void *)XPAR_MYINTC_BASEADDR); /* Connect uart interrupt handler that will be called when an interrupt * for the uart occurs */ XIntc_RegisterHandler(XPAR_MYINTC_BASEADDR, XPAR_MYINTC_MYUART_INTERRUPT_INTR, (XInterruptHandler)uart_int_handler, (void *)XPAR_MYUART_BASEADDR); /* Start the interrupt controller */ XIntc_mMasterEnable(XPAR_MYINTC_BASEADDR); /* Set the gpio as output on
R 346 Chapter 23: Interrupt Management www.xilinx.com 1-800-255-7778 Embedded System Tools Guide (EDK 6.2i) UG111 (v1.
