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XAPP1178 (v2.0) January 23, 2015 www.xilinx.com 1

Summary

This reference design demonstrates the implementation of the Vivado® design tools IP

DisplayPort (DP) system that includes policy maker features and a DisplayPort controller. There

are two hardware designs (Tcl files) provided with this reference design separately for single

stream transport (SST) and multi-stream transport (MST) modes of operation. Video pattern

generators are used to generate the traffic for testing. The reference design is created and built

using the Vivado Design Suite. Instructions are included for building the hardware, building the

software with local drivers for DisplayPort, and testing the design on the Xilinx KC705 board

with the generated bitstream and Executable Linker format (ELF) files. In addition, the

ready_for_download folder in the package contains the ready-made tested bitstreams and

elf files for both SST and MST modes.

The Tcl file provided under the hw folder can be executed in the Vivado design tools to create

the project and generate the bitstream. The Software Development Kit (SDK) workspace that

contains the source code and BSP folder that can be re-built to create the elf file is provided

under the sw directory.

IMPORTANT: This reference design does not demonstrate the audio functionality of DisplayPort.

Objective

This application note describes how to implement a DisplayPort core transmit system and how

to bring up the source core through the initialization steps such as training the main link,

setting up the source core registers and monitoring and taking appropriate action on Hot Plug

Detect (HPD) assertion. It showcases a system transporting video data from the Xilinx

DisplayPort transmit core to a DisplayPort capable monitor for both SST and MST modes of

operation. A DisplayPort source policy maker is implemented on the KC705 Evaluation Board,

which includes the MicroBlaze™ processor, and DisplayPort core, as well as video pattern

generators. The block diagram of the reference design is shown in Figure 1.

Application Note: Kintex®-7 Family

XAPP1178 (v2.0) January 23, 2015

DisplayPort Transmit Reference Design

for SST and MST Modes

Authors: Dinesh Kumar, Siva Rajesh Jarugula

Summary of content (27 pages)

PAGE 1
Application Note: Kintex®-7 Family XAPP1178 (v2.0) January 23, 2015 DisplayPort Transmit Reference Design for SST and MST Modes Authors: Dinesh Kumar, Siva Rajesh Jarugula Summary This reference design demonstrates the implementation of the Vivado® design tools IP DisplayPort (DP) system that includes policy maker features and a DisplayPort controller.
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Hardware Requirements X-Ref Target - Figure 1 y/ϰͲ>ŝƚĞ 'LVSOD\3RUW 9LYDGR 'HVLJQ 7RROV ,3 7UDQVPLW 6RXUFH &RUH $;, /LWH 9LGHR &ORFN *HQHUDWRU y/ϰͲ>ŝƚĞ 'LVSOD\3RUW 6LQNV 0RQLWRUV dǆͺǀŝĚͺĐůŬ 0LFUR%OD]H 3URFHVVRU 9LGHR 3DWWHUQ *HQHUDWRU V ,3 ,QWHJUDWRU 6\VWHP ; Figure 1: Reference Design Block Diagram Hardware Requirements This reference design requires the following hardware: • Kintex-7 KC705, revision 1.
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Package Details Package Details This section shows the directory structure of the design files provided along with the application note. All files are in the DP_Tx_Xapp directory. The user directory path under which this DP_Tx_Xapp is copied to is being referred as "XAPP1178" in the rest of this application note. You can download the Reference Design Files for this application note from the Xilinx website.
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Description • sst: This folder contains the hw and sw sub directories for SST mode operation. The hw directory contains the mst.tcl file that can be sourced from the Vivado design tools to create the bitstream. The sw directory contains the already exported software project workspace that can be opened using SDK. This workspace will have an exported hardware definition file, board support package created with a local DP drivers repository, and source code to test the DP design.
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Description Hardware Block Diagram Figure 3 shows the hardware architecture of the reference design. The design uses the Vivado Design Suite IP integrator tool, a block-based design, and assembly tool. The IP integrator is used to integrate many of the key blocks of the design into a subsystem. The IP integrator subsystem consists of the MicroBlaze processor, AXI interconnect IP, MIG 7 series IP and other AXI4-Lite peripherals.
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Description Pattern Generators The video pattern generator has an advanced peripheral bus (APB) bus interface that is connected to the AXI APB Bridge for processor communication. The registers available in the video pattern generator are listed in Table 1. The video timing information is programmed by writing into the registers. Eight standard pixel patterns can be generated by the module.
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Description DisplayPort Transmit Core Customization The MicroBlaze processor interfaces with the DisplayPort core through the AXI4-Lite interface. This enables the software application and policy maker to do the TX initialization, initiate and maintain the main link through register writes and reads. This reference design customizes the DisplayPort core to work as transmit source code with DP v1.2 enabled, Max Bits per color of 16, Quad pixel enable, Max number of lanes as 4, and Max Link rate of 5.4 Gb/s.
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Description Figure 4 shows the application flow for SST mode. X-Ref Target - Figure 4 067 +DUGZDUH LV LQ 667 067 PRGH" *R WR 067 IORZ 667 ,QLWLDOL]H '3 7; FRUH *HW 5; FDSDELOLWLHV EK 'HFLGH RQ UHVROXWLRQ EDVHG RQ (',' z ^ 8VHU LQSXW UHFHLYHG" $GMXVW OLQN FRQILJXUDWLRQ EDVHG RQ XVHU LQSXW (VWDEOLVK OLQN 6HW 06$ YDOXHV IRU HQDEOHG VWUHDP &RQILJXUH YLGHR VWUHDP VRXUFH (QDEOH PDLQ OLQN ; Figure 4: XAPP1178 (v2.0) January 23, 2015 Application Flow for SST Mode www.xilinx.
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Description Figure 5 shows the application flow for MST mode. X-Ref Target - Figure 5 667 *R WR 667 IORZ +DUGZDUH LV LQ 667 067 PRGH" &RQILJXUH YLGHR VWUHDPV 067 ,QLWLDOL]H '3 7; FRUH *HW 067 &DSDELOLW\ RI 5; DQG 5; FDSDELOLWLHV EK 6WUHDP WR VLQN PDSSLQJ $OORFDWH SD\ORDG WDEOHV z ^ 8VHU LQSXW UHFHLYHG" $GMXVW OLQN FRQILJXUDWLRQ EDVHG RQ XVHU LQSXW (VWDEOLVK OLQN (QDEOH PDLQ OLQN 5XQ WRSRORJ\ GLVFRYHU\ 6HW 06$ YDOXHV IRU HQDEOHG VWUHDPV ; Figure 5: XAPP1178 (v2.
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Description Initialization In the first stage, from the Vivado tools exported hardware parameter definition file (xparameters.h), the application finds if the hardware design has MST enabled or not. The application executes the corresponding sub-routines. The DisplayPort source core is set up and initialized in the following sequence. 1. Keep the physical layer (PHY) in reset. 2. Disable transmitter. 3. Set clock divider. 4. Set DisplayPort clock speed. 5. Bring the PHY out of reset. 6.
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Description DisplayPort Transmitter Software Drivers The software application provided in this application note is built upon the DisplayPort transmitter drivers which has the link policy maker and stream policy maker features implemented. Local driver repository (v3.0) provided in the application package overwrites the DisplayPort drivers (v2.0) that exist in the Vivado Design Suite. DisplayPort drivers also use the common video libraries present with the DP drivers.
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Description DPCD reads/writes: • AUX reads/writes to DPCD: Using AUX transactions, a DPTX device can read a DPRX DisplayPort Configuration Data (DPCD). Each DPRX device has a 20-bit address space that the 8-bit DPCD registers are mapped to. The DPCD contains registers that allow a DPRX to declare its capabilities and status, and allows a DPTX device to control and configure the DPRX. • I2C-over-AUX: A DPTX can also determine a sink device display identity and capabilities.
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Setup Details Hot-plug-detect (HPD) handling HPD events can be detected in the form of connection/disconnection or pulse events. The events can be polled for, or interrupts can be enabled in the system and handlers can be set in the application. When the HPD signal is connected to an interrupt controller in the system, the SW driver steers the flow of software to run an HPD pulse handler if an HPD pulse occurs, or an HPD event handler if an HPD event occurs.
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Setup Details X-Ref Target - Figure 6 Figure 6: Hardware Setup 5. Connect the power supply cable and turn on the KC705 board. 6. Start a Hyper Terminal program on the host PC with the following settings: ° Baud rate: 9600 ° Data Bits: 8 ° Parity: None ° Stop Bits: 1 ° Flow Control: None XAPP1178 (v2.0) January 23, 2015 www.xilinx.
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How to Run How to Run How to Build the Reference Design This section describes how to build the reference design for both hardware and software. Before beginning, unzip the reference design into a local directory (referred to as XAPP1178 in the rest of the steps). If you want to build the hardware design and SDK workspace instead of using the bitstream and elf files from the ready_for_download folder, follow these steps.
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How to Run X-Ref Target - Figure 8 Figure 8: Base and High Addresses of the IP Cores Present in IP Integrator System for SST Mode Open the Exported Hardware Workspace in SDK 1. After the bitstream generation is complete, open the already exported hardware workspace in SDK. 2. Open the xsdk GUI. 3. Give the workspace path as XAPP1178/DP_Tx_Xapp/sst/sw and click OK.
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How to Run Note: You can also export the generated hardware to SDK and build the project and create the elf file afresh instead of loading the SDK work space provided in the package. Refer to the SDK user guide to export hardware from the Vivado design tools, load the driver repository, create empty application, import the source code provide under the XAPP1178/DP_Tx_Xapp/sst/sw/src folder, build the project and create the elf file.
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How to Run For MST mode, the application finds the number of sinks connected (the maximum will be 4) and displays video on all the sink monitors. IMPORTANT: Ensure that you are selecting the resolution and BPC values that are not beyond the sink monitor max supported values.
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How to Run X-Ref Target - Figure 11 Figure 11: : Change bits per color 3. Select options for combinations of lane count and link rates. X-Ref Target - Figure 12 Figure 12: Change Number of Lanes and Link Rate 4. Change pattern for the selected stream. X-Ref Target - Figure 13 Figure 13: Change Pattern 5. Display MSA (Multi Stream Attribute) Values for TX. XAPP1178 (v2.0) January 23, 2015 www.xilinx.
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How to Run X-Ref Target - Figure 14 Figure 14: XAPP1178 (v2.0) January 23, 2015 MSA Values for TX www.xilinx.
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How to Run 6. Display Extended Display Identification Data (EDID) information of the sink monitor. Note: It might not be reliable information for some monitors. X-Ref Target - Figure 15 Figure 15: XAPP1178 (v2.0) January 23, 2015 Display EDID Configurations (Part 1) www.xilinx.
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How to Run X-Ref Target - Figure 16 Figure 16: XAPP1178 (v2.0) January 23, 2015 Display EDID Configurations (Part 2) www.xilinx.
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How to Run 7. Display Link Configuration Status and user selected resolution, BPC values. X-Ref Target - Figure 17 Figure 17: Link and Lane Status 8. Display DPCD configurations of the sink monitor. X-Ref Target - Figure 18 Figure 18: XAPP1178 (v2.0) January 23, 2015 Display DPCD Configurations www.xilinx.
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Results 9. Perform AUX read for the set of registers by giving a 4-bit Hex offset address of the first register. X-Ref Target - Figure 19 Figure 19: Auxiliary Read Results The display should come on the connected sink monitor. Similarly for MST, the display should come on all the sink monitors that are connected in daisy-chain mode by DisplayPort cables (Limited to four displays).
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Results SST mode is tested with the Samsung- U28D590D ultra HD resolution monitor. MST mode is tested with four streams Dell U2713H, DELL U3014T, and Asus-PQ321Q connected in daisy-chain mode with HD video on all four displays. X-Ref Target - Figure 20 Figure 20: Hardware Setup and Results for SST Mode with Ultra HD Resolution X-Ref Target - Figure 21 Figure 21: Hardware Setup and Results for MST Mode with HD Resolution on 4 Streams XAPP1178 (v2.0) January 23, 2015 www.xilinx.
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Troubleshooting Troubleshooting This section provides debugging steps for issues in the policy maker software. There are help menu options provided to read MSA values, EDID information, Link and Lane status, and DPCD status. There is also another option to enter the four-digit hexadecimal register offset and the number of registers to read the DPCD register values through the aux interface. Enter the four-digit hexadecimal register offset for any DPCD registers, to know the exact status of the system.
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Revision History Revision History The following table shows the revision history for this document. Date Version Description of Revisions 01/23/2015 2.0 Updated the Reference Design Files link on page 3. 12/19/2014 2.0 Updated the application note to test the latest DisplayPort version of 5.0 with Vivado design tools 2014.4. The application tests both MST and SST modes of the DisplayPort core and uses the DisplayPort drivers that implement the policy maker features. 09/13/2013 1.