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Description

XAPP1178 (v2.0) January 23, 2015 www.xilinx.com 5

Hardware Block Diagram

Figure 3 shows the hardware architecture of the reference design. The design uses the Vivado

Design Suite IP integrator tool, a block-based design, and assembly tool. The IP integrator is

used to integrate many of the key blocks of the design into a subsystem. The IP integrator

subsystem consists of the MicroBlaze processor, AXI interconnect IP, MIG 7 series IP and other

AXI4-Lite peripherals. The IP integrator sub-system is integrated in the top module along with

DisplayPort IP and custom design sources for video pattern generator and video clock

generator. The MicroBlaze processor changes the DisplayPort core configuration over the

AXI4-Lite interface based on the user application.

Clocking

The DisplayPort core uses the following clock domains:

• The processor and the AXI domain operate at 50 MHz.

• The TED FMCH DP2 card provides a 135 MHZ reference clock for the transceivers. This clock

is then used to derive the link clock for the DisplayPort based on the link rate selected.

• A transmit video clock is generated using the Video Clock generator IP which takes the link

clock as the reference clock.

X-Ref Target - Fi gure 3

Figure 3: Hardware Architecture for both MST and SST Modes

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