Product guide

Description
XAPP1178 (v2.0) January 23, 2015 www.xilinx.com 6
Pattern Generators
The video pattern generator has an advanced peripheral bus (APB) bus interface that is
connected to the AXI APB Bridge for processor communication. The registers available in the
video pattern generator are listed in Table 1. The video timing information is programmed by
writing into the registers. Eight standard pixel patterns can be generated by the module.
• Vesa logical link control (LLC) pattern
• Vesa pattern three bars
•Vesa color squares
•Flat red
•Flat blue
• Flat green
• Flat yellow
•Color bars
Table 1: Pattern Generator Registers
Address Read/Write Description
0x000 R/W Bit 0 = Enable video output.
Bit 1 = SW reset of the pattern generator.
0x004 R/W Bit 0 = VSYNC polarity.
0x008 R/W Bit 0 = HSYNC polarity.
0x00C R/W Bit 0 = DE polarity.
0x010 R/W Bits 8:0 = VSYNC width.
0x014 R/W Bits 8:0 = Vertical back porch.
0x018 R/W Bits 8:0 = Vertical front porch.
0x01C R/W Bits 10:0 = Vertical resolution.
0x020 R/W Bits 8:0 = HSYNC width.
0x024 R/W Bits 8:0 = Horizontal back porch.
0x028 R/W Bits 8:0 = Horizontal front porch.
0x02C R/W Bits 10:0 = Horizontal resolution.
0x104 R/W Bits 7:0 = TX Video clock M value. Used for video clock synthesis.
Video_clock = lnk_clk * M/D.
0x108 R/W Bits 7:0 = TX Video clock D value. Used for video clock synthesis.
Video_clock = lnk_clk * M/D.
0x200 R Bits 11:0 = VSYNC counter current count.
0x204 R Bits 11:0 = HSYNC counter current count.
0x208 R Bits 11:0 = Data enable counter current count.