Product guide

Description
XAPP1178 (v2.0) January 23, 2015 www.xilinx.com 7
DisplayPort Transmit Core Customization
The MicroBlaze processor interfaces with the DisplayPort core through the AXI4-Lite interface.
This enables the software application and policy maker to do the TX initialization, initiate and
maintain the main link through register writes and reads. This reference design customizes the
DisplayPort core to work as transmit source code with DP v1.2 enabled, Max Bits per color of 16,
Quad pixel enable, Max number of lanes as 4, and Max Link rate of 5.4 Gb/s.
The DisplayPort physical layer (PHY) is customized to use the bidirectional AUX channel
interface signals: aux_tx_io_p and aux_tx_io_n. The four transceivers for the four
high-speed lanes are mapped to the four GTX transceivers in the FMC HPC (MGT_BANK_118) on
the KC705 board. The software application gives you the option to select fewer numbers of
lanes (1 or 2 lanes) to be used.
Software Application
The reference design includes a software application running on a MicroBlaze processor to
initialize and maintain the DisplayPort link. The software application uses the DisplayPort
drivers v3.0 provided with this package under the common folder. This application provides an
interactive UART console through which you can test the system at different modes of
operation. You are given the flexibility to debug the application by reading the DisplayPort AUX
registers.