Product specifications

CN333 Data Sheet
Revision 1.0, January 5, 2005 -31- Device 0 Function 0 Register Descriptions - AGP
Device 0 Function 0 Registers – AGP
Device 0 Function 0 Header Registers
All registers are located in PCI configuration space. They
should be programmed using PCI configuration mechanism 1
through CF8 / CFC with bus number, function number and
device number equal to zero and function number equal to 0.
(CN333 does not support external AGP port)
Offset 1-0 - Vendor ID (1106h) .........................................RO
15-0 ID Code (reads 1106h to identify VIA Technologies)
Offset 3-2 - Device ID (0259h) ...........................................RO
15-0 ID Code (reads 0259h to identify the CN333 NB)
Offset 5-4 –Command (0006h) .........................................RW
15-10 Reserved ........................................ always reads 0
9 Fast Back-to-Back Cycle Enable ........................ RO
0 Fast back-to-back transactions only allowed to
the same agent........................................default
1 Fast back-to-back transactions allowed to
different agents
8 SERR# Enable...................................................... RO
0 SERR# driver disabled...........................default
1 SERR# driver enabled
7 Address / Data Stepping...................................... RO
0 Device never does stepping....................default
1 Device always does stepping
6 Parity Error Response........................................RW
0 Ignore parity errors & continue..............default
1 Take normal action on detected parity errors
5 VGA Palette Snoop.............................................. RO
0 Treat palette accesses normally..............default
1 Don’t respond to palette accesses on PCI bus
4 Memory Write and Invalidate Command ......... RO
0 Bus masters must use Mem Write..........default
1 Bus masters may generate Mem Write & Inval
3 Special Cycle Monitoring .................................... RO
0 Does not monitor special cycles.............default
1 Monitors special cycles
2 PCI Bus Master.................................................... RO
0 Never behaves as a bus master
1 Can behave as a bus master....................default
1 Memory Space...................................................... RO
0 Does not respond to memory space
1 Responds to memory space....................default
0 I/O Space .......................................................... RO
0 Does not respond to I/O space ..............default
1 Responds to I/O space
Offset 7-6 – Status (0210h)............................................ RWC
15 Detected Parity Error
0 No parity error detected......................... default
1 Error detected in either address or data phase.
This bit is set even if error response is disabled
(command register bit-6). ..... write one to clear
14 Signaled System Error (SERR# Asserted)
........................................always reads 0
13 Signaled Master Abort
0 No abort received .................................. default
1 Transaction aborted by the master ...................
................................... write one to clear
12 Received Target Abort
0 No abort received .................................. default
1 Transaction aborted by the target .....................
................................... write one to clear
11 Signaled Target Abort .......................always reads 0
0 Target Abort never signaled
10-9 DEVSEL# Timing
00 Fast
01 Medium ...................................always reads 01
10 Slow
11 Reserved
8 Data Parity Error Detected
0 No data parity error detected ................. default
1 Error detected in data phase. Set only if error
response enabled via command bit-6 = 1 and
the North Bridge was initiator of the operation
in which the error occurred... write one to clear
7 Fast Back-to-Back Capable ...............always reads 0
6 User Definable Features.....................always reads 0
5 66MHz Capable..................................always reads 0
4 Supports New Capability list.............always reads 1
3-0 Reserved ........................................always reads 0
Offset 8 - Revision ID (0nh) .............................................. RO
7-0 Chip Revision Code........................always reads 0nh
Offset 9 - Programming Interface (00h) .......................... RO
7-0 Interface Identifier .........................always reads 00h
Offset A - Sub Class Code (00h)....................................... RO
7-0 Sub Class Code .......reads 00 to indicate Host Bridge
Offset B - Base Class Code (06h)...................................... RO
7-0 Base Class Code.. reads 06 to indicate Bridge Device
Offset D - Latency Timer (00h) ....................................... RW
Specifies the latency timer value in PCI bus clocks.
7-3 Guaranteed Time Slice for CPU ...............default=0
2-0 Reserved (fixed granularity of 8 clks) .. always read 0
Bits 2-1 are writeable but read 0 for PCI specification
compatibility. The programmed value may be read
back in Rx75[6-4] (PCI Arbitration 1).