Product specifications

CN333 Data Sheet
Revision 1.0, January 5, 2005 -64- Device 0 Function 7 Register Descriptions – V-Link
Offset 75 - PCI Arbitration 1 (00h)..................................RW
7 Arbitration Mode
0 REQ-based (arbitrate at end of REQ#) ..default
1 Frame-based (arbitrate at FRAME# assertion)
6-4 CPU Latency
3 Reserved ........................................ always reads 0
2-0 PCI Master Bus Time-Out
(force into arbitration after a period of time)
000 Disable ...................................................default
001 1x16 PCICLKs
010 2x16 PCICLKs
011 3x16 PCICLKs
100 4x16 PCICLKs
... ...
111 7x16 PCICLKs
Offset 76 - PCI Arbitration 2 (00h)................................. RW
7 I/O Port 22 Access
0 CPU access to I/O address 22h is passed on to
the PCI bus ............................................ default
1 CPU access to I/O address 22h is processed
internally
6 Reserved ........................................always reads 0
5-4 Master Priority Rotation Control
00 Disable................................................... default
01 Grant to CPU after every PCI master grant
10 Grant to CPU after every 2 PCI master grants
11 Grant to CPU after every 3 PCI master grants
Setting 01
: the CPU will always be granted access
after the current bus master completes, no matter how
many PCI masters are requesting.
Setting 10
: if other PCI masters are requesting during
the current PCI master grant, the highest priority
master will get the bus after the current master
completes, but the CPU will be guaranteed to get the
bus after that master completes.
Setting 11
: if other PCI masters are requesting, the
highest priority will get the bus next, then the next
highest priority will get the bus, then the CPU will
get the bus.
In other words, with the above settings, even if
multiple PCI masters are continuously requesting the
bus, the CPU is guaranteed to get access after every
master grant (01), after every other master grant (10)
or after every third master grant (11).
3-2 Select REQn# to REQ4# mapping
00 REQ4#................................................... default
01 REQ0#
10 REQ1#
11 REQ2#
1 Reserved ........................................always reads 0
0 REQ4# is High Priority Master
0 Disable................................................... default
1 Enable