Instruction Manual

UG:013 vicorpower.com Applications Engineering: 800 927.9474 Page 9
Schematic
Schematic for half-chip and full-chip PRM
®
evaluation board is same.
Figure 3a.
PRM evaluation board
schematic
J11
J15
2220
C1 5
2220
C1 6
2220
C1 7
1210
C1 1
1210
C1 2
1210
C1 3
J16
J12
1 2 3 4 5 6 7 8 9 10
J13
1
2
3
4
5
6
7
8
9
1
0
J
1
3
VC_OUT
1210
C1 4
1 2 3 4 5 6 7 8 9 10
1
2
3
4
5
6
7
8
9
1
0
J10
CONNECTOR FRONT VIEW
9
10
7
8
5 6
3 4
1
2
VTM_-IN
TP32 TP31
TP30
TP33
+SENSE -SENSE
VTM_ TM
VTM_ PC
VTM_IM
TP26
TP25
-OUT
-OUT
VC VC
-OUT
-OUT
+OUT
+OUT
+OUT
+OUT
9
10
7
8
5 6
3 4
1
2
-S
+S
V_TM V_PC
VTM_-IN
V_IM
VT
TSOT 23_6
3 1 2
6 5 4
V OUT V- +IN
V+
RG
-IN
U10
0603
C18
TP28
TP29
R26 1206
TP27
EN ABLE
SHARE/CO NTROL NODE
SGND
ENABLETRIMAL
SHAR E/CONTROL NODE
REF/REF_EN VCVTVAUX
0603
R10
0603
R11
0603
R12
0603
R13
0603
R14
0603
R15
0603
R16 R17
0603
SGND
TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17
SIGNAL PIN TEST POINTS AND FIXED RESIST ORS
2
3 1
S11
S
G
D
SOT 23_3
Q10
0603 R21
SGND
TP23
TP24
VCC
SGND
ON/OFF CONTROL
TP35
TP36
IMON
IFB
R18
0603
TP18
ON
SGND
SHARE/CONTROL NODE
TRIM
EAO
IF B
IMON
LOCAL SENSE_ +
PRM_ +OUT
+SENSE_B -SENSE_B
+SENSE -SENSE
MODE SELEC T
TRIM
AL
+IN -IN
+OUT
-OUT
IF B
VC VT
REF/
REF_EN
VAUX
SHARE/
CONTROL NODE
PR M
ENABLE
DA
CL
SGND
PS10
PRM2 _HALF_ JLEAD
PRM_ +OUT
SGND
TRIM
AL
VAUX
REF/REF_EN
IFB
VC_OUT
VC
1206 R22
1206
R24
1206
R23
J14
-OUT
H37
H38
REF/REF_ EN
VAUX
VCC
REF_ EN_ B
VT
VTM_TM
R19
0603
R20
0603
NC1 NC2
TP19 TP20
NC1 NC2
CURRENT SENSE AMPLIFIER
SGND
123456 789
H28
H35
H29
H36
H31H30
H13 H14 H15 H16 H17 H18
H10 H11 H12
H19 H20
H23
H26
H24
H25
H27
TP45
TP47 TP49 TP51
TP53
TP55
TP56
TP58
TP57
TP59
TP46
TP48
TP50
TP52
TP54
TP60
TP34
L1 0
L1 1
GND
HS10
H32
H33
-OUT
H34
i
PIN
i
PIN
i
PIN
i
POUT
i
POUT
i
POUT
i+S
i-S
iPOU T
TP22
TP21
H22
H21
10
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
1110
19
20
S10 SW_21910MST
iPOU T
H57
H58
Cin
Cout2220
C2 5
2220
C2 6
2512 R25
F10
TP62
TP61
TP63
TP64
TP65
TP66
TP67
TP68
LOCAL SENSE (Single Ended)
REMOTE SENSE (Dierential) SLAVE
ADAPTIVE LOOP
DEFAULT