User guide

ManualsBrandsVIP ManualsMedia ConverterVideo Converter

Video and Image Processing Suite User

Guide

Send Feedback

UG-VIPSUITE

2015.05.04

101 Innovation Drive

San Jose, CA 95134

www.altera.com

Summary of content (310 pages)

PAGE 1
Video and Image Processing Suite User Guide Subscribe Send Feedback UG-VIPSUITE 2015.05.04 101 Innovation Drive San Jose, CA 95134 www.altera.
PAGE 2
TOC-2 Contents Video and Image Processing Suite Overview..................................................... 1-1 Release Information.....................................................................................................................................1-3 Device Family Support................................................................................................................................ 1-4 Latency................................................................................
PAGE 3
TOC-3 Modules for Clocked Video Input II IP Core........................................................................................ 4-15 Clocked Video Interface Parameter Settings......................................................................................... 4-18 Clocked Video Interface Signals.............................................................................................................. 4-26 Clocked Video Interface Control Registers............................................
PAGE 4
TOC-4 Color Space Conversion Parameter Settings..........................................................................................10-4 Color Space Conversion Signals.............................................................................................................. 10-8 Color Space Conversion Control Registers..........................................................................................10-10 Control Synchronizer IP Core..........................................................
PAGE 5
TOC-5 Gamma Corrector IP Core................................................................................ 15-1 Gamma Corrector Parameter Settings....................................................................................................15-1 Gamma Corrector Signals........................................................................................................................ 15-2 Gamma Corrector Control Registers...........................................................................
PAGE 6
TOC-6 Avalon-ST Video Monitor IP Core................................................................... 21-1 Packet Visualization.................................................................................................................................. 21-2 Monitor Settings........................................................................................................................................ 21-3 Avalon-ST Video Monitor Parameter Settings............................................
PAGE 7
1 Video and Image Processing Suite Overview 2015.05.04 UG-VIPSUITE Send Feedback Subscribe The Altera® Video and Image Processing Suite collection of IP cores ease the development of video and image processing designs. You can use these IP cores in a wide variety of image processing and display applications. Attention: Altera has scheduled the following IP cores for product obsolescence and will discontinue support for it.
PAGE 8
1-2 IP Core (3) (4) UG-VIPSUITE 2015.05.
PAGE 9
UG-VIPSUITE 2015.05.04 Release Information 1-3 Release Information The following table lists information about this release of the Video and Image Processing Suite. Table 1-2: Release Information Item Version Description 15.
PAGE 10
1-4 UG-VIPSUITE 2015.05.04 Device Family Support Device Family Support The table below lists the device support information for the Video and Image Processing Suite IP cores.
PAGE 11
UG-VIPSUITE 2015.05.04 Latency 1-5 Latency You can use the latency information to predict the approximate latency between the input and the output of your video processing pipeline. The latency is described using one or more of the following measures: • • • • the number of progressive frames the number of interlaced fields the number of lines when less than a field of latency a small number of cycles O (cycles) Note: O refers to a small number of clock cycles, and is not of zero value.
PAGE 12
1-6 UG-VIPSUITE 2015.05.04 Latency IP Core Clocked Video Input II Clocked Video Output/ Clocked Video Output II Note: Add 1 cycle if you turned on the Allow color planes in sequence input parameter.
PAGE 13
UG-VIPSUITE 2015.05.
PAGE 14
1-8 UG-VIPSUITE 2015.05.
PAGE 15
UG-VIPSUITE 2015.05.04 1-9 In-System Performance and Resource Guidance Table 1-5: Performance and Resource Data Using Arria V Devices The following data are obtained through a 4K test design example using an Arria V device (5AGXFB3H4F35C4). The general settings for the design is 8 bits per color plane; 2 pixels in parallel. The target fMAX is 148.5 MHz.
PAGE 16
1-10 UG-VIPSUITE 2015.05.04 In-System Performance and Resource Guidance Table 1-6: Performance and Resource Data Using Cyclone V Devices The following data are obtained through a video design example using a Cyclone V device (5CGTFD9E5F35C7). The general setting for the design is 8 bits per color plane. The target fMAX is 100 MHz.
PAGE 17
UG-VIPSUITE 2015.05.
PAGE 18
1-12 UG-VIPSUITE 2015.05.
PAGE 19
UG-VIPSUITE 2015.05.04 Stall Behavior and Error Recovery IP Core 2D FIR Filter Stall Behavior • Has a delay of a little more than N–1 lines between data input and output in the case of a N×N 2D FIR Filter. • Delay caused by line buffering internal to the IP core. 1-13 Error Recovery • Resolution is not configurable at run time. • Does not read the control packets passed through it.
PAGE 20
1-14 UG-VIPSUITE 2015.05.04 Stall Behavior and Error Recovery IP Core Alpha Blending Mixer/ Mixer II Altera Corporation Stall Behavior Error Recovery The Alpha Blending Mixer IP core processes video packets from the background layer until the end of packet Between frames, the IP core processes nonis received. image data packets from its input layers in sequential order.
PAGE 21
UG-VIPSUITE 2015.05.04 Stall Behavior and Error Recovery IP Core Chroma Resampler Stall Behavior All modes stall for a few cycles between frames and between lines. Latency from input to output varies depending on the operation mode of the IP core. • The only modes with latency of more than a few cycles are 4:2:0 to 4:2:2 and 4:2:0 to 4:4:4—corresponding to one line of 4:2:0 data • The quantities of data input and output are not equal because this is a ratechanging function.
PAGE 22
1-16 UG-VIPSUITE 2015.05.04 Stall Behavior and Error Recovery IP Core Clocked Video Output/ Clocked Video Output II Color Plane Sequencer Stall Behavior Error Recovery • Dictated by outgoing video. • Receiving an early endofpacket signal— the IP core resynchronizes • If its input FIFO is empty, during the outgoing video data to the horizontal and vertical blanking periods incoming video data on the next start the IP core stalls and does not take in of packet it receives. any more video data.
PAGE 23
UG-VIPSUITE 2015.05.04 Stall Behavior and Error Recovery IP Core Stall Behavior 1-17 Error Recovery Control Synchronizer • Stalls for several cycles between packets. • Processes video packets until the IP core receives an endofpacket signal • Stalls when it enters a triggered state —the image width, height and while it writes to the Avalon-MM Slave interlaced fields of the control data ports of other IP cores.
PAGE 24
1-18 UG-VIPSUITE 2015.05.04 Stall Behavior and Error Recovery IP Core Deinterlacer II/ Broadcast Deinterlacer Stall Behavior Stores input video fields in the external memory and concurrently uses these input video fields to construct deinterlaced frames. • Stalls up to 50 clock cycles for the first output frame. • Additional delay of one line for second output frame because the IP core generates the last line of the output frame before accepting the first line of the next input field.
PAGE 25
UG-VIPSUITE 2015.05.04 Stall Behavior and Error Recovery IP Core Frame Buffer/ Frame Buffer II Stall Behavior 1-19 Error Recovery • May stall frequently and read or write • Does not rely on the content of the less than once per clock cycle during control packets to determine the size control packet processing. of the image data packets.
PAGE 26
1-20 UG-VIPSUITE 2015.05.04 Stall Behavior and Error Recovery IP Core Scaler II Stall Behavior Error Recovery • The ratio of reads to writes is • Receiving an early endofpacket proportional to the scaling ratio and signal at the end of an input line—the occurs on both a per-pixel and a per-line IP core stalls its input but continues basis. writing data until it has sent on further output line.
PAGE 27
UG-VIPSUITE 2015.05.04 Stall Behavior and Error Recovery IP Core Stall Behavior 1-21 Error Recovery Enabling run-time control of resolutions affects stalling between frames: • With no run-time control: about 10 cycles of delay before the stall behavior begins, and about 20 cycles of further stalling between each output line. • With run-time control of resolutions: about additional 25 cycles of delay between frames.
PAGE 28
Interfaces 2 2015.05.04 UG-VIPSUITE Subscribe Send Feedback The IP cores in the Video and Image Processing Suite use standard interfaces for data input and output, control input, and access to external memory. These standard interfaces ensure that video systems can be quickly and easily assembled by connecting IP cores together. The IP cores use the following types of interface: • Avalon-ST interface—a streaming interface that supports backpressure.
PAGE 29
2-2 UG-VIPSUITE 2015.05.04 Video Formats The Clocked Video Input and Clocked Video Output IP cores also have external interfaces that support clocked video standards. These IP cores can connect between the function’s Avalon-ST interfaces and functions using clocked video standards such as BT.656. Related Information Avalon Interface Specifications Provides more information about these interface types.
PAGE 30
UG-VIPSUITE 2015.05.
PAGE 31
2-4 UG-VIPSUITE 2015.05.04 Video Formats Figure 2-3: Interlaced Frame Format Horizontal Sync Height F0 Active Picture Field Width Width Vertical Sync F1 Active Picture Height Horizontal Blanking F0 Vertical Blanking Vertical Blanking For CVI and CVO IP cores, the BT656 and BT1120 formats use time reference signal (TRS) codes in the video data to mark the places where synchronization information is inserted in the data.
PAGE 32
UG-VIPSUITE 2015.05.04 Video Formats 2-5 Clocked Video Output IP Cores For the embedded synchronization format, the CVO IP cores insert the horizontal and vertical syncs and field into the data stream during the horizontal blanking period. The IP cores create a sample for each clock cycle on the vid_data bus. There are two extra signals only used when connecting to the SDI IP core. They are vid_trs, which is high during the 3FF sample of the TRS, and vid_ln, which produces the current SDI line number.
PAGE 33
2-6 UG-VIPSUITE 2015.05.04 Video Formats The CVI IP cores extract any ancillary packets from the Y channel during the vertical blanking. Ancillary packets are not extracted from the horizontal blanking. • Clocked Video Input IP core—The extracted packets are produced through the CVI IP cores’ AvalonST output with a packet type of 13 (0xD). • Clocked Video Input II IP core— The extracted packets are stored in a RAM in the IP core, which can be read via the control interface.
PAGE 34
UG-VIPSUITE 2015.05.04 2-7 Avalon-ST Video Protocol Figure 2-6: Separate Synchronization Signals Timing Diagram vid_data D0 D1 DN Dn+1 Dn+2 vid_de/vid_datavalid (1) vid_v_sync vid_h_sync vid_f (1): vid_datavalid: Clocked Video Output IP core vid_de: Clocked Video Input IP core The CVI IP cores only read the vid_data, vid_de, vid_h_sync, vid_v_sync, and vid_f signals when vid_datavalid is 1.
PAGE 35
2-8 UG-VIPSUITE 2015.05.04 Avalon-ST Video Protocol Table 2-3: Avalon-ST Video Protocol Parameters Parameter Values IP Cores Frame Width/ Height Interlaced/ Progressive Bits per Color Sample Color Pattern 2D FIR Filter User-defined— Progressive through parameter editor User-defined— One, two, or three through channels in sequence.
PAGE 36
UG-VIPSUITE 2015.05.
PAGE 37
2-10 UG-VIPSUITE 2015.05.04 Avalon-ST Video Protocol Parameter Values IP Cores Interlacer Frame Width/ Height Run-time controlled Interlaced/ Progressive Bits per Color Sample Color Pattern Progressive; User-defined— One, two or three interlaced data is through channels in sequence either discarded parameter editor or parallel.
PAGE 38
UG-VIPSUITE 2015.05.
PAGE 39
2-12 UG-VIPSUITE 2015.05.04 Static Parameters of Video Data Packets Color Pattern The organization of the color plane samples within a video data packet is referred to as the color pattern. This parameter also defines the bit width of symbols for all packet types on a particular Avalon-ST interface. An Avalon-ST interface must be at least four bits wide to fully support the Avalon-ST Video protocol.
PAGE 40
UG-VIPSUITE 2015.05.04 Static Parameters of Video Data Packets 2-13 Figure 2-10: Vertically Subsampled Y'CbCr The figure below samples from the upper color plane transmitted on even rows and samples from the lower plane transmitted on odd rows. Plane for even rows Y Cb Cr Y Plane for odd rows Table 2-5: Examples of Static Avalon-ST Video Data Packet Parameters The table below lists the static parameters and gives some examples of how you can use them.
PAGE 41
2-14 UG-VIPSUITE 2015.05.04 Static Parameters of Video Data Packets Parameter Bits per Color Sample Recommended Color Patterns Parallel Y’CbCr Sequence Cb Cr Y Y Cr Cb 4:2:2 Y’CbCr Y Y Cb Y Cr Y Cb Cr Following these recommendations, ensures compatibility minimizing the need for color pattern rearranging. These color patterns are designed to be compatible with common clocked video standards where possible. Note: If you must rearrange color patterns, use the Color Plane Sequencer IP core.
PAGE 42
UG-VIPSUITE 2015.05.04 Control Data Packets 2-15 Structure of Video Data Packets Figure 2-11: Parallel Color Pattern This figure shows the structure of a video data packet using a set parallel color pattern and bits per pixel per color plane.
PAGE 43
2-16 UG-VIPSUITE 2015.05.04 Control Data Packets The width and height values are the dimensions of the video data packets that follow. The width refers to the width in pixels of the lines of a frame. The height refers to the number of lines in a frame or field. For example, a field of interlaced 1920×1080 (1080i) would have a width of 1920 and a height of 540, and a frame of 1920×1080 (1080p) would have a width of 1920 and a height of 1080.
PAGE 44
UG-VIPSUITE 2015.05.04 Control Data Packets 2-17 Parameters Description Type Width Height Interlacin g 15 640 480 0000 The frames that follow are progressive with a resolution of 640×480. The frames were deinterlaced using F0 as the last field. 15 640 480 0001 The frames that follow are progressive with a resolution of 640×480. The frames were deinterlaced using F1 as the last field. 15 640 240 1000 The fields that follow are 640 pixels wide and 240 pixels high.
PAGE 45
2-18 UG-VIPSUITE 2015.05.04 Control Data Packets Structure of a Control Data Packet A control data packet complies with the standard of a packet type identifier followed by a data payload. The data payload is split into nibbles of 4 bits; each data nibble is part of a symbol. If the width of a symbol is greater than 4 bits, the function does not use the most significant bits of the symbol. Order Symbol Order Symbol 1 width[15..12] 6 height[11..8] 2 width[11..8] 7 height[7..4] 3 width[7..
PAGE 46
UG-VIPSUITE 2015.05.04 Ancillary Data Packets 2-19 Figure 2-15: One Symbol in Parallel Control data, reference numbers to Table 4-5 Start 15 1 2 3 4 5 6 7 8 End 9 Control data packet type identifier (4 bits in least significant symbol, X’s for unused symbols) Ancillary Data Packets Ancillary data packets send ancillary packets between IP cores.
PAGE 47
2-20 UG-VIPSUITE 2015.05.04 Transmission of Avalon-ST Video Over Avalon-ST Interfaces To make the protocol flexible and extensible, the Video and Image Processing IP cores obey the following rules about propagating non-video packets: • The IP cores must propagate user packets until they receive an end of packet signal. Nevertheless, the IP cores that buffer packets into external memory may introduce a maximum size due to limited storage space.
PAGE 48
UG-VIPSUITE 2015.05.04 Packet Transfer Examples Signal Width 1 endofpacket 2-21 Direction Source to Sink Related Information Avalon Interface Specifications Provides more information about these interface types. Packet Transfer Examples All packets are transferred using the Avalon-ST signals in the same way. Example 1 (Data Transferred in Parallel) This example shows the transfer of a video data packet in to and then out of a generic IP core that supports the Avalon-ST Video protocol.
PAGE 49
2-22 UG-VIPSUITE 2015.05.04 Packet Transfer Examples Figure 2-16: Timing Diagram Showing R’G’B’ Transferred in Parallel The figure below shows how the first few pixels of a frame are processed. 1. 2. 4. 3. 5. 6. n. 7.
PAGE 50
UG-VIPSUITE 2015.05.04 Packet Transfer Examples 3. 4. 5. 6. 7. 8. 2-23 ready latency in the Avalon Interface Specifications. All the Avalon-ST interfaces used by the Video and Image Processing Suite IP cores have a ready latency of one clock cycle. The source feeding the input port sets din_valid to logic '1' indicating that it is sending data on the data port and sets din_startofpacket to logic '1' indicating that the data is the first value of a new packet.
PAGE 51
2-24 UG-VIPSUITE 2015.05.04 Packet Transfer Examples Figure 2-17: Timing Diagram Showing R’G’B’ Transferred in Sequence The figure shows how a number of pixels from the middle of a frame are processed. 2. 1. 3. 4. 5. 6. 7. 8. 9.
PAGE 52
UG-VIPSUITE 2015.05.04 Avalon-MM Slave Interfaces 2-25 Example 3 (Control Data Transfer) Figure 2-18: Timing Diagram Showing Control Packet Transfer This figure shows the transfer of a control packet for a field of 720×480 video (with field height 240).
PAGE 53
2-26 Avalon-MM Slave Interfaces UG-VIPSUITE 2015.05.04 The first two registers of every control interface perform the following two functions (the others vary with each control interface): • Register 0 is the Go register. Bit zero of this register is the Go bit. A few cycles after the function comes out of reset, it writes a zero in the Go bit (remember that all registers in Avalon-MM control slaves power up in an undefined state).
PAGE 54
UG-VIPSUITE 2015.05.04 Specification of the Type of Avalon-MM Slave Interfaces 2-27 You can build logic (or program a Nios II processor) to control the gamma corrector as follows: 1. Set the Go bit to zero. This causes the IP core to stop processing at the end of the current frame. 2. Poll the Status bit until the IP core sets it to zero. This occurs at the end of the current frame, after the IP core has stopped processing data. 3. Update the gamma look-up table. 4. Set the Go bit to one.
PAGE 55
2-28 UG-VIPSUITE 2015.05.04 Avalon-MM Master Interfaces Signal Width Direction waitrequest 1 Output irq(6) 1 Output Note: The list does not include clock and reset signal types. The Video and Image Processing Suite IP cores do not support Avalon-MM interfaces in multiple clock domains. Instead, the Avalon-MM slave interfaces must operate synchronously to the main clock and reset signals of the IP core. The Avalon-MM slave interfaces must operate synchronously to this clock.
PAGE 56
UG-VIPSUITE 2015.05.04 Buffering of Non-Image Data Packets in Memory 2-29 Note: The clock and reset signal types are optional. The Avalon-MM master interfaces can operate on a different clock from the IP core and its other interfaces by selecting the relevant option in the parameter editor when and if it is available. A master interface that only performs write transactions do not require the read-only signals. A master interface that only performs read transactions do not require the write-only signals.
PAGE 57
3 Getting Started 2015.05.04 UG-VIPSUITE Subscribe Send Feedback The Video and Image Processing Suite IP cores are installed as part of the Quartus II installation process. IP Catalog and Parameter Editor The Video and Image Processing Suite IP cores are available only through the Qsys IP Catalog. The Qsys IP Catalog (Tools > Qsys) and parameter editor help you easily customize and integrate IP cores into your project.
PAGE 58
3-2 Specifying IP Core Parameters and Options UG-VIPSUITE 2015.05.04 Specifying IP Core Parameters and Options Follow these steps to specify IP core parameters and options. 1. In the Qsys IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. The parameter editor appears. 2. Specify a top-level name for your custom IP variation. This name identifies the IP core variation files in your project.
PAGE 59
UG-VIPSUITE 2015.05.04 OpenCore Plus IP Evaluation 3-3 Related Information • Altera Licensing Site • Altera Software Installation and Licensing Manual OpenCore Plus IP Evaluation Altera's free OpenCore Plus feature allows you to evaluate licensed MegaCore IP cores in simulation and hardware before purchase. You need only purchase a license for MegaCore IP cores if you decide to take your design to production.
PAGE 60
Clocked Video Interface IP Cores 4 2015.05.04 UG-VIPSUITE Subscribe Send Feedback The Clocked Video Interface IP cores convert clocked video formats (such as BT656, BT1120, and DVI) to Avalon-ST Video; and vice versa. You can configure these IP cores at run time using an Avalon-MM slave interface.
PAGE 61
4-2 UG-VIPSUITE 2015.05.04 Clocked Video Input Format Detection Output IP cores still accept data on the Avalon-ST Video interface for as long as there is space in the input FIFO. The sequence for starting the output of the IP core: 1. Write a 1 to Control register bit 0. 2. Read Status register bit 0. When this bit is 1, the IP core produces data or video. This occurs on the next start of frame or field boundary. Note: For CVI IP cores, the frame or field matches the Field order parameter settings.
PAGE 62
UG-VIPSUITE 2015.05.04 Clocked Video Input Format Detection Format 4-3 Description Picture height (in lines) • The IP core counts the total number of lines per frame or field, and the number of lines in the active picture period. • One full frame or field of video is required before the IP core can determine the height. Interlaced/Progressive • The IP core detects whether the incoming video is interlaced or progressive. • If it is interlaced, separate height values are stored for both fields.
PAGE 63
4-4 UG-VIPSUITE 2015.05.04 Clocked Video Input Format Detection • Clocked Video Input IP core After reset, if the IP core has not yet determined the format of the incoming video, it uses the values specified under the Avalon-ST Video Initial/Default Control Packet section in the parameter editor. After determining an aspect of the incoming videos format, the IP core enters the value in the respective register, sets the registers valid bit in the Status register, and triggers the respective interrupts.
PAGE 64
UG-VIPSUITE 2015.05.04 Interrupts 4-5 Interrupts The CVI IP cores produce a single interrupt line. Table 4-5: Internal Interrupts The table below lists the internal interrupts of the interrupt line. IP Core Internal Interrupts Description Status update interrupt Triggers when a change of resolution in the incoming video is detected.
PAGE 65
4-6 Clocked Video Output Video Modes UG-VIPSUITE 2015.05.04 The CVO IP cores can be configured to support between 1 to 14 different modes and each mode has a bank of registers that describe the output frame. • Clocked Video Output IP Core • When the IP core receives a new control packet on the Avalon-ST Video input, it searches the mode registers for a mode that is valid. The valid mode must have a field width and height that matches the width and height in the control packet.
PAGE 66
UG-VIPSUITE 2015.05.04 4-7 Clocked Video Output Video Modes Figure 4-1: Progressive Frame Parameters The figure shows how the register values map to the progressive frame format.
PAGE 67
4-8 UG-VIPSUITE 2015.05.04 Clocked Video Output Video Modes Figure 4-2: Interlaced Frame Parameters The figure shows how the register values map to the interlaced frame format.
PAGE 68
UG-VIPSUITE 2015.05.04 Interrupts 4-9 • For Clocked Video Output IP Core, the following steps reconfigure mode 1: 1. Write 0 to the Mode1 Valid register. 2. Write to the Mode 1 configuration registers. 3. Write 1 to the Mode1 Valid register. The mode is now valid and can be selected. • For Clocked Video Output II IP Core, the following steps reconfigure mode 1: 1. Write 1 to the Bank Select register. 2. Write 0 to the Mode N Valid configuration register. 3.
PAGE 69
4-10 UG-VIPSUITE 2015.05.04 Generator Lock A CVI IP core can take in the locked PLL clock and the SOF signal and align the output video to these signals. This produces an output video frame that is synchronized to the incoming video frame. Clocked Video Input IP Core For Clocked Video Input IP core, you can compare vcoclk_div to refclk_div, using a phase frequency detector (PFD) that controls a voltage controlled oscillator (VCXO).
PAGE 70
UG-VIPSUITE 2015.05.04 Underflow and Overflow 4-11 Figure 4-3: Genlock Example Configuration The figure shows an example of a Genlock configuration for Clocked Video Input IP core.
PAGE 71
4-12 UG-VIPSUITE 2015.05.04 Timing Constraints Note: For Clocked Video Output IP core, you can also read the current level of the FIFO from the Used Words register. This register is not available for Clocked Video Output II IP core. Overflow The FIFO can accommodate any bursts as long as the input rate of the upstream Avalon-ST Video components is equal to or higher than that of the incoming clocked video. If this is not the case, the FIFO overflows.
PAGE 72
UG-VIPSUITE 2015.05.04 Handling Ancillary Packets 4-13 AFD Extractor (Clocked Video Input) When the output of the CVI IP cores connects to the input of the AFD Extractor, the AFD Extractor removes any ancillary data packets from the stream and checks the DID and secondary DID (SDID) of the ancillary packets contained within each ancillary data packet. If the packet is an AFD packet (DID = 0x41, SDID = 0x5), the extractor places the contents of the ancillary packet into the AFD Extractor register map.
PAGE 73
4-14 UG-VIPSUITE 2015.05.04 Handling Ancillary Packets Figure 4-4: Ancillary Packet Register The figure below shows the position of the ancillary packets. The different colors indicate different ancillary packets.
PAGE 74
UG-VIPSUITE 2015.05.04 Modules for Clocked Video Input II IP Core 4-15 Table 4-8: AFD Inserter Register Map Address 0 Register Control Description • When bit 0 is 0, the core discards all packets. • When bit 0 is 1, the core passes through all non-ancillary packets. 1 — Reserved. 2 — Reserved. 3 AFD Bits 0-3 contain the active format description code. 4 AR Bit 0 contains the aspect ratio code. 5 Bar data flags Bits 0-3 contain the bar data flags to insert.
PAGE 75
4-16 UG-VIPSUITE 2015.05.04 Modules for Clocked Video Input II IP Core Figure 4-5: Block Diagram for Clocked Video Input II IP Core The figure below shows a block diagram of the Clocked Video Input II IP core architecture.
PAGE 76
UG-VIPSUITE 2015.05.04 Modules for Clocked Video Input II IP Core Modules Resolution_detection 4-17 Description • This module uses the h_sync, v_sync, de, and f signals to detect the resolution of the incoming video.
PAGE 77
4-18 UG-VIPSUITE 2015.05.04 Clocked Video Interface Parameter Settings Modules Av_st_output Description • This module creates the control packets, from the detected resolution read from the control module, and the video packets, from the active picture data read from the write_buffer_fifo module. • The packets are sent to the Video Output Bridge which turns them into Avalon-ST video packets.
PAGE 78
UG-VIPSUITE 2015.05.04 Clocked Video Interface Parameter Settings Parameter Value 4-19 Description Width 32–65,536, Default = 1920 Specify the image width to be used when no format is automatically detected. Height – frame/field 0 32–65,536, Default = 1080 Specify the image height to be used when no format is automatically detected. Height – field 1 32–65,536, Default = 1080 Specify the image height for interlaced field 1 to be used when no format is automatically detected.
PAGE 79
4-20 UG-VIPSUITE 2015.05.04 Clocked Video Interface Parameter Settings Parameter Value Description Sync signals • Embedded in video • On separate wires Specify whether to embed the synchroniza‐ tion signal in the video stream or provide on a separate wire. Allow color planes in sequence input On or Off Turn on if you want to allow run-time switching between sequential and parallel color plane transmission formats. The format is controlled by the vid_hd_sdn signal.
PAGE 80
UG-VIPSUITE 2015.05.04 Clocked Video Interface Parameter Settings Parameter Use control port Value On or Off 4-21 Description Turn on to use the optional stop/go control port. Table 4-12: Clocked Video Output Parameter Settings Parameter Value Description Select preset to load • • • • • Image width/Active pixels 32–65536, Default = 1920 Specify the image width by choosing the number of active pixels.
PAGE 81
4-22 UG-VIPSUITE 2015.05.04 Clocked Video Interface Parameter Settings Parameter Value Description Frame/Field 1: Ancillary packet insertion line 32–65536, Default = 0 Specify the line where ancillary packet insertion starts. Frame/Field 1: Horizontal blanking 32–65536, Default = 0 Specify the size of the horizontal blanking period in pixels for Frame/Field 1. Frame/Field 1: Vertical blanking 32–65536, Default = 0 Specify the size of the vertical blanking period in pixels for Frame/Field 1.
PAGE 82
UG-VIPSUITE 2015.05.04 Clocked Video Interface Parameter Settings Parameter Value 4-23 Description Pixel FIFO size 32–(memory limit), Default = 1920 Specify the required FIFO depth in pixels, (limited by the available on-chip memory). FIFO level at which to start output 0–(memory limit), Default = 0 Specify the fill level that the FIFO must have reached before the output video starts.
PAGE 83
4-24 UG-VIPSUITE 2015.05.04 Clocked Video Interface Parameter Settings Parameter Value Description Allow output of color planes in sequence On or Off • Turn on if you want to allow run-time switching between sequential formats, such as NTSC, and parallel color plane transmission formats, such as 1080p. The format is controlled by the ModeXControl registers. • Turn off if you are using multiple pixels in parallel.
PAGE 84
UG-VIPSUITE 2015.05.04 Clocked Video Interface Parameter Settings Parameter Value 4-25 Description Separate syncs only - Frame/ Field 1: Vertical back porch 32–65536, Default = 36 Specify the number of lines in the vertical back porch in pixels for Frame/Field 1. Interlaced and Field 0: F rising edge line 32–65536, Default = 0 Specify the line when the rising edge of the field bit occurs for Interlaced and Field 0.
PAGE 85
4-26 UG-VIPSUITE 2015.05.04 Clocked Video Interface Signals Clocked Video Interface Signals Table 4-14: Control Signals for CVI and CVO IP Cores Signal av_address Direction Input Description control slave port Avalon-MM address bus. Specifies a word offset into the slave address space. Note: Present only if you turn on Use control port. Input av_read control slave port Avalon-MM read signal. When you assert this signal, the control port drives new data onto the read data bus.
PAGE 86
UG-VIPSUITE 2015.05.04 Clocked Video Interface Signals Signal Direction Input av_read 4-27 Description control slave port Avalon-MM read signal. When you assert this signal, the control port drives new data onto the read data bus. Note: Present only if you turn on Use control port. av_readdata Output control slave port Avalon-MM read data bus. These output lines are used for read transfers. Note: Present only if you turn on Use control port.
PAGE 87
4-28 UG-VIPSUITE 2015.05.04 Clocked Video Interface Signals Signal Direction Description is_sop Output dout port Avalon-ST startofpacket signal. This signal is asserted when the IP core is starting a new frame. is_valid Output dout port Avalon-ST valid signal. This signal is asserted Output Clocked video overflow signal. A signal corresponding to the overflow sticky bit of the Status register synchronized to vid_clk.
PAGE 88
UG-VIPSUITE 2015.05.04 Clocked Video Interface Signals Signal vid_hd_sdn Direction Input 4-29 Description Clocked video color plane format selection signal. This signal distinguishes between sequential (when low) and parallel (when high) color plane formats. Note: For run-time switching of color plane transmission formats mode only. vid_v_sync Input Clocked video vertical synchronization signal. Assert this signal during the vertical synchronization period of the video stream.
PAGE 89
4-30 UG-VIPSUITE 2015.05.04 Clocked Video Interface Signals Signal dout_valid status_update_int Direction Description Output dout port Avalon-ST valid signal. This signal is asserted Output control slave port Avalon-MM interrupt signal. When when the IP core produces data. asserted, the status registers of the IP core have been updated and the master must read them to determine what has occurred. Note: Present only if you turn on Use control port. vid_clk Input Clocked video clock.
PAGE 90
UG-VIPSUITE 2015.05.04 Clocked Video Interface Signals Signal vid_hd_sdn Direction Input 4-31 Description Clocked video color plane format selection signal . This signal distinguishes between sequential (when low) and parallel (when high) color plane formats. Note: For run-time switching of color plane transmission formats mode only. vid_std Input Video standard bus. Can be connected to the rx_std signal of the SDI IP core (or any other interface) to read from the Standard register.
PAGE 91
4-32 UG-VIPSUITE 2015.05.04 Clocked Video Interface Signals Signal is_eop is_ready is_sop is_valid underflow Direction Description Input dout port Avalon-ST endofpacket signal. This signal is Output dout port Avalon-ST ready signal. This signal is asserted Input dout port Avalon-ST startofpacket signal. Assert this asserted when the downstream device is ending a frame. when the IP core function is able to receive data. signal when the downstream device is starting a new frame.
PAGE 92
UG-VIPSUITE 2015.05.04 Clocked Video Interface Signals Signal vid_f Direction Output 4-33 Description Clocked video field signal. For interlaced input, this signal distinguishes between field 0 and field 1. For progressive video, this signal is unused. Note: For separate synchronization mode only. vid_h Output Clocked video horizontal blanking signal. This signal is asserted during the horizontal blanking period of the video stream. Note: For separate synchronization mode only.
PAGE 93
4-34 UG-VIPSUITE 2015.05.04 Clocked Video Interface Signals Table 4-19: Clocked Video Output II Signals Signal Direction Description main_reset_reset Input The IP core asynchronously resets when you assert this signal. You must deassert this signal synchronously to the rising edge of the clock signal. main_clock_clk Input The main system clock. The IP core operates on the rising edge of this signal. din_data Input din port Avalon-ST data bus.
PAGE 94
UG-VIPSUITE 2015.05.04 Clocked Video Interface Signals Signal status_update_int Direction Output 4-35 Description control slave port Avalon-MM interrupt signal. When asserted, the status registers of the IP core have been updated and the master must read them to determine what has occurred. Note: Present only if you turn on Use control port. vid_clk Input Clocked video clock. All the video output signals are synchronous to this clock. vid_data Output Clocked video data bus.
PAGE 95
4-36 UG-VIPSUITE 2015.05.04 Clocked Video Interface Control Registers Signal Direction Output vid_trs Description Clocked video time reference signal (TRS) signal. Used with the SDI IP core to indicate a TRS, when asserted. Note: For embedded synchronization mode only. Output vid_v Clocked video vertical blanking signal. This signal is asserted during the vertical blanking period of the video stream. Note: For separate synchronization mode only.
PAGE 96
UG-VIPSUITE 2015.05.04 Clocked Video Interface Control Registers Address 1 Register Status 4-37 Description • Bit 0 of this register is the Status bit. • This bit is asserted when the CVI IP core is producing data. • Bits 5, 2, and 1 of the Status register are unused. • Bits 6, 4, and 3 are the resolution valid bits. • When bit 3 is asserted, the SampleCount register is valid. • When bit 4 is asserted, the F0LineCount register is valid. • When bit 6 is asserted, the F1LineCount register is valid.
PAGE 97
4-38 UG-VIPSUITE 2015.05.04 Clocked Video Interface Control Registers Address Register 7 Total Sample Count 8 F0 Total Line Count 9 F1 Total Line Count 10 Standard 11 SOF Sample 12 SOF Line 13 Refclk Divider Description The detected sample count of the video streams including blanking. The detected line count of the video streams F0 field including blanking. The detected line count of the video streams F1 field including blanking. The contents of the vid_std signal.
PAGE 98
UG-VIPSUITE 2015.05.04 Clocked Video Interface Control Registers Address 1 Register Status 4-39 Description • Bit 0 of this register is the Status bit. • This bit is asserted when the CVI IP core is producing data. • Bits 6–1 of the Status register are unused. • Bit 7 is the interlaced bit: • When asserted, the input video stream is interlaced. • Bit 8 is the stable bit: • When asserted, the input video stream has had a consistent line length for two of the last three lines.
PAGE 99
4-40 UG-VIPSUITE 2015.05.04 Clocked Video Interface Control Registers Address Register 9 F1 Total Line Count 10 Standard 11 SOF Sample 12 SOF Line 13 Refclk Divider 14 Reserved 15 Ancillary Packet 15 + Depth of ancillary memory Description The detected line count of the video streams F1 field including blanking. The contents of the vid_std signal. Start of frame line register. The line upon which the SOF occurs measured from the rising edge of the F0 vertical sync. SOF line register.
PAGE 100
UG-VIPSUITE 2015.05.04 Clocked Video Interface Control Registers Address 1 Register Status 4-41 Description • Bit 0 of this register is the Status bit. • This bit is asserted when the CVO IP core is producing data. • Bit 1 of the Status register is unused. • Bit 2 is the underflow sticky bit. • When bit 2 is asserted, the output FIFO has underflowed. The underflow sticky bit stays asserted until a 1 is written to this bit. • Bit 3 is the frame locked bit.
PAGE 101
4-42 UG-VIPSUITE 2015.05.04 Clocked Video Interface Control Registers Address 10 11 12 13 14 15 16 17 18 19 Register Description Mode1 Horizontal Sync Length Video mode 1 horizontal synchronization length. Specifies the length of the horizontal synchronization length in samples. Mode1 Horizontal Blanking Video mode 1 horizontal blanking period. Specifies the length of the horizontal blanking period in samples. Mode1 Vertical Front Porch Video mode 1 vertical front porch.
PAGE 102
UG-VIPSUITE 2015.05.04 Clocked Video Interface Control Registers Address 27 Register Mode1 F0 Ancillary Line 28 Mode1 Valid 29 ModeN Control ... 4-43 Description The line in field F0 to start inserting ancillary data packets. Video mode 1 valid. Set to indicate that this mode is valid and can be used for video output. ... Table 4-23: Clocked Video Output II Registers The rows in the table are repeated in ascending order for each video mode. All of the ModeN registers are write only.
PAGE 103
4-44 UG-VIPSUITE 2015.05.04 Clocked Video Interface Control Registers Address 2 Register Interrupt Description Bits 2 and 1 are the interrupt status bits: • When bit 1 is asserted, the status update interrupt has triggered. • When bit 2 is asserted, the locked interrupt has triggered. • The interrupts stay asserted until a 1 is written to these bits. 3 Video Mode Match 4 Bank Select 5 ModeX Control One-hot register that indicates the video mode that is selected.
PAGE 104
UG-VIPSUITE 2015.05.04 Clocked Video Interface Control Registers Address 15 16 17 18 19 Register Mode1 F0 Vertical Front Porch Mode1 F0 Vertical Sync Length Mode1 F0 Vertical Blanking 4-45 Description Video mode 1 field 0 vertical front porch (interlaced video only). Specifies the length of the vertical front porch in lines. Video mode 1 field 0 vertical synchronization length (interlaced video only). Specifies the length of the vertical synchronization length in lines.
PAGE 105
4-46 UG-VIPSUITE 2015.05.
PAGE 106
5 2D FIR Filter IP Core 2015.05.04 UG-VIPSUITE Subscribe Send Feedback The 2D FIR Filter IP core performs 2D convolution using matrices of 3×3, 5×5, or 7×7 coefficients. The 2D FIR Filter IP core retains full precision throughout the calculation while making efficient use of FPGA resources. With suitable coefficients, the IP core performs operations such as sharpening, smoothing, and edge detection.
PAGE 107
5-2 UG-VIPSUITE 2015.05.04 Coefficient Precision Coefficient Precision The 2D FIR Filter IP core requires a fixed point type to be defined for the coefficients. The user-entered coefficients (shown as white boxes in the parameter editor) are rounded to fit in the chosen coefficient fixed point type (shown as purple boxes in the parameter editor). Result to Output Data Type Conversion After calculation, the fixed point type of the results must be converted to the integer data type of the output.
PAGE 108
UG-VIPSUITE 2015.05.04 2D FIR IP Core Parameter Settings Parameter Input data type: Bits per pixel per color plane Value 4-20, Default = 8 5-3 Description Select the number of bits per pixel (per color plane). Note: You can specify a higher precision output by increasing Bits per pixel per color plane and Move binary point right. Input data type: Data type • Unsigned • Signed Select if you want the input to be unsigned or signed 2's complement.
PAGE 109
5-4 UG-VIPSUITE 2015.05.04 2D FIR Filter Signals Parameter Output data type: Min Move binary point right Value Description 1,048,575 to -524,288, Set output range minimum value. Default = 0 Note: The output is constrained to fall in the specified range of maximum and minimum guard band values. -16 to +16, Default = 0 Specify the number of places to move the binary point. This can be useful if you require a wider range output on an existing coefficient set.
PAGE 110
UG-VIPSUITE 2015.05.04 2D FIR Filter Control Registers Signal Direction din_ready din_startofpacket din_valid dout_data dout_endofpacket dout_ready dout_startofpacket dout_valid 5-5 Description Output din_N port Avalon-ST ready signal. The IP core asserts Input din_N port Avalon-ST startofpacket signal. This signal Input din_N port Avalon-ST valid signal. This signal identifies Output dout port Avalon-ST data bus. This bus enables the this signal when it is able to receive data.
PAGE 111
5-6 UG-VIPSUITE 2015.05.04 2D FIR Filter Control Registers Address n Register Coefficient n Description The coefficient at position: • Row (where 0 is the top row of the kernel) is the integer value through the truncation of (n–2) / (filter kernel width) . • Column (where 0 is the far left row of the kernel) is the remainder of (n–2) / (filter kernel width).
PAGE 112
6 Video Mixing IP Cores 2015.05.04 UG-VIPSUITE Subscribe Send Feedback The Video Mixing IP cores mix together multiple image layers . This run-time control is partly provided by an Avalon-MM slave port with registers for the location, and on or off status of each foreground layer. The dimensions of each layer are then specified by Avalon-ST Video control packets. Note: It is expected that each foreground layer fits in the boundaries of the background layer.
PAGE 113
6-2 UG-VIPSUITE 2015.05.04 Alpha Blending background layer. The IP core treats the non-image data packets from the foreground layers differently depending on their type. • Control packets (type 15)— processed to extract the width and height of each layer and are discarded on the fly. • Other/user packets (types 1–14)—propagated unchanged. The second step corresponds to the usual behavior of other Video and Image Processing IP cores that have an Avalon-MM slave interface.
PAGE 114
UG-VIPSUITE 2015.05.04 Video Mixing Parameter Settings 6-3 at the system-level if erroneous pixels have to be discarded. The IP core ignores all non-image data packets (including control packets) and discards them just before the processing of a frame starts. The valid range of alpha coefficients is 0 to 1, where 1 represents full translucence, and 0 represents fully opaque. For n-bit alpha values (RGBAn) coefficients range from 0 to 2n–1.
PAGE 115
6-4 UG-VIPSUITE 2015.05.04 Video Mixing Parameter Settings Parameter Value Description Number of color planes in parallel 1, 2, 3 Select the number of color planes in parallel. Number of layers being mixed 2–12 Select the number of image layers to overlay. The higher number layers are mixed on top of the lower number layers. The background layer is always layer 0.
PAGE 116
UG-VIPSUITE 2015.05.04 Video Mixing Signals Parameter Value 6-5 Description Pattern • Color bars • Uniform background Select the pattern you want to use for the background test pattern layer. Uniform values 0-255; Default = 0 (R/ Y); 128 (G/Cb/B/Cr) When pattern is uniform background, you can specify the individual R'G'B' or Y' Cb' Cr' values depending on the currently selected color space.
PAGE 117
6-6 UG-VIPSUITE 2015.05.04 Video Mixing Signals Signal din_N_valid dout_N_data dout_N_endofpacket dout_N_ready dout_N_startofpacket dout_N_valid Direction Description Input din_N port Avalon-ST valid signal. This signal identifies Output dout port Avalon-ST data bus. This bus enables the Output dout_N port Avalon-ST endofpacket signal. This signal Input the cycles when the port must input data. transfer of pixel data out of the IP core. marks the end of an Avalon-ST packet.
PAGE 118
UG-VIPSUITE 2015.05.04 Video Mixing Signals Signal control_read Direction Output 6-7 Description control slave port Avalon-MM read signal. When you assert this signal, the control port produces new data at readdata. Output control slave port Avalon-MM readdata bus. The IP control_readdatavalid Output control slave port Avalon-MM readdata bus. The IP core asserts this signal when the readdata bus contains valid data in response to the read signal.
PAGE 119
6-8 UG-VIPSUITE 2015.05.04 Video Mixing Control Registers Signal Direction Description dout_N_ready Input dout_N port Avalon-ST ready signal. The downstream device asserts this signal when it is able to receive data. dout_N_startofpacket Output dout_N port Avalon-ST startofpacket signal. This signal Output dout_N port Avalon-ST valid signal. The IP core asserts dout_N_valid marks the start of an Avalon-ST packet. this signal when it produces data.
PAGE 120
UG-VIPSUITE 2015.05.04 Video Mixing Control Registers 6-9 Table 6-7: Mixer II Control Register Map The table below describes the control register map for Mixer II IP core. Address Register Description 0 Control Bit 0 of this register is the Go bit, all other bits are unused. Setting this bit to 0 causes the IP core to stop the next time control information is read. 1 Status Bit 0 of this register is the Status bit, all other bits are unused. 2 Interrupt Unused.
PAGE 121
6-10 UG-VIPSUITE 2015.05.04 Video Mixing Control Registers Address Register Description 20 Input 3 enable • Set to bit 0 to enable Input 3. • Set to bit 1 to enable consume mode. 21 Reserved Reserved for future use. 22 Reserved Reserved for future use.
PAGE 122
Chroma Resampler IP Core 7 2015.05.04 UG-VIPSUITE Subscribe Send Feedback The Chroma Resampler IP core resamples video data to and from common sampling formats. The human eye is more sensitive to brightness than tone. Taking advantage of this characteristic, video transmitted in the Y’CbCr color space often subsamples the color components (Cb and Cr) to save on data bandwidth.
PAGE 123
7-2 UG-VIPSUITE 2015.05.04 4:4:4 to 4:2:2 Figure 7-1: Resampling 4.4.4 to a 4.2.2 Image The figure below shows the location of samples in a co-sited 4:2:2 image. 3 5 7 + + + 6 + + 4 + + 2 + + + + + 8 + 3 + 2 + + + 1 + +++ + = Y’ = Cb = Cr = CbCr = Y’CbCr Sample No 1 4 The Chroma Resampler IP core supports only the cosited form of horizontal resampling—the form for 4:2:2 data in ITU Recommendation BT.601, MPEG-2, and other standards.
PAGE 124
UG-VIPSUITE 2015.05.04 Vertical Resampling (4:2:0) 7-3 Figure 7-2: 4:2:2 Data at an Edge Transition The figure below shows 4:2:2 data at an edge transition. Without taking any account of the luma, the interpolation to produce chroma values for sample 4 would weight samples 3 and 5 equally. From the luma, you can see that sample 4 falls on an the low side of an edge, so sample 5 is more significant than sample 3.
PAGE 125
7-4 UG-VIPSUITE 2015.05.04 Chroma Resampler Parameter Settings Note: All input data samples must be in unsigned format. If the number of bits per pixel per color plane is N, this means that each sample consists of N bits of data which are interpreted as an unsigned binary number in the range [0, 2N–1]. All output data samples are also in the same unsigned format.
PAGE 126
UG-VIPSUITE 2015.05.04 Chroma Resampler Signals 7-5 Chroma Resampler Signals Table 7-2: Chroma Resampler Signals Signal Direction Description clock Input The main system clock. The IP core operates on the rising edge of this signal. reset Input The IP core asynchronously resets when this signal is high. You must deassert this signal synchronously to the rising edge of the clock signal. din_data Input din port Avalon-ST data bus.
PAGE 127
8 Video Clipping IP Cores 2015.05.04 UG-VIPSUITE Send Feedback Subscribe The Video Clipping IP cores clip video streams. You can configure these IP cores at compile time, or run time using an Avalon-MM slave interface. The Video Clipping IP cores—Clipper and Clipper II—provide a means to select an active area from a video stream and discard the remainder.
PAGE 128
8-2 UG-VIPSUITE 2015.05.04 Video Clipping Parameter Settings Parameter Value Description Number of color planes in parallel 1–3, Default = 1 Select the number of color planes in parallel. Include Avalon-MM interface On or Off Turn on if you want to specify clipping offsets using the Avalon-MM interface. Clipping method • Offsets • Rectangle Specify the clipping area as offsets from the edge of the input area or as a fixed rectangle.
PAGE 129
UG-VIPSUITE 2015.05.04 Video Clipping Parameter Settings 8-3 Table 8-2: Clipper II Parameter Settings Parameter Value Description Maximum input frame width 32–4096, Default = 1920 Specify the maximum frame width of the clipping rectangle for the input field (progres‐ sive or interlaced). Maximum input frame height 32–4096, Default = 1080 Specify the maximum height of the clipping rectangle for the input field (progressive or interlaced).
PAGE 130
8-4 UG-VIPSUITE 2015.05.04 Video Clipping Signals Parameter Value 0–1080, Default = 10 Right offset Description Specify the x coordinate for the right edge of the clipping rectangle. 0 is the right edge of the input area. Note: The left and right offset values must be less than or equal to the input image width. Bottom offset 0–1080, Default = 10 Specify the y coordinate for the bottom edge of the clipping rectangle. 0 is the bottom edge of the input area.
PAGE 131
UG-VIPSUITE 2015.05.04 Video Clipping Signals Signal Direction Description dout_endofpacket Output dout port Avalon-ST endofpacket signal. This signal marks the end of an Avalon-ST packet. dout_ready Input dout port Avalon-ST ready signal. The downstream Output dout port Avalon-ST startofpacket signal. This signal dout_startofpacket dout_valid Output 8-5 device asserts this signal when it is able to receive data. marks the start of an Avalon-ST packet. dout port Avalon-ST valid signal.
PAGE 132
8-6 UG-VIPSUITE 2015.05.04 Video Clipping Control Registers Signal Direction Input control_byteenable Description control slave port Avalon-MM byteenable bus. This bus enables specific byte lane or lanes during transfers. Each bit in byteenable corresponds to a byte in writedata and readdata. During writes, byteenable specifies which bytes are being written to; other bytes are ignored by the slave. Slaves that simply return readdata with no side effects are free to ignore byteenable during reads.
PAGE 133
UG-VIPSUITE 2015.05.04 Video Clipping Control Registers Address 2 Register Left Offset 8-7 Description The left offset, in pixels, of the clipping window/rectangle. Note: The left and right offset values must be less than or equal to the input image width. 3 Right Offset or Width In clipping window mode, the right offset of the window. In clipping rectangle mode, the width of the rectangle. Note: The left and right offset values must be less than or equal to the input image width.
PAGE 134
8-8 UG-VIPSUITE 2015.05.04 Video Clipping Control Registers Address 4 Register Right Offset or Width Description In clipping window mode, the right offset of the window. In clipping rectangle mode, the width of the rectangle. Note: The left and right offset values must be less than or equal to the input image width. 5 Top Offset The top offset, in pixels, of the clipping window/rectangle. Note: The top and bottom offset values must be less than or equal to the input image height.
PAGE 135
9 Color Plane Sequencer IP Core 2015.05.04 UG-VIPSUITE Subscribe Send Feedback The Color Plane Sequencer IP core changes how color plane samples are transmitted across the AvalonST interface. You can configure the channel order in sequence or in parallel. The Color Plane Sequencer IP core rearranges the color pattern used to transmit Avalon-ST Video data packets over an Avalon-ST connection (stream).
PAGE 136
9-2 UG-VIPSUITE 2015.05.04 Rearranging Color Patterns Figure 9-1: Example of Combining Color Patterns The figure shows an example of combining and rearranging two color patterns.
PAGE 137
UG-VIPSUITE 2015.05.04 Splitting and Duplicating 9-3 data. Altera recommends that when you define a packet type where the length is variable and meaningful, you send the length at the start of the packet. Splitting and Duplicating The Color Plane Sequencer IP core splits a single Avalon-ST Video input stream into two Avalon-ST Video output streams..
PAGE 138
9-4 UG-VIPSUITE 2015.05.04 Subsampled Data Subsampled Data In addition to fully sampled color patterns, the Color Plane Sequencer IP core also supports 4:2:2 subsampled data. For the Color Plane Sequencer IP core to support 4:2:2 subsampled data, you can configure the IP core with two color patterns in sequence, so that subsampled planes can be specified individually.
PAGE 139
UG-VIPSUITE 2015.05.04 Color Plane Sequencer Signals Parameter Value 9-5 Description dout0: Color planes in parallel 1, 2, 3, 4 Select the number of color planes in parallel for input port dout0. dout0: Halve control packet width On or Off Turn on to halve the Avalon-ST Video control packet width for output port dout0. Turn on this parameter when stream contains two subsampled channels.
PAGE 140
9-6 UG-VIPSUITE 2015.05.04 Color Plane Sequencer Signals Signal Direction Description reset Input The IP core asynchronously resets when this signal is high. You must deassert this signal synchronously to the rising edge of the clock signal. dinN_data Input dinN port Avalon-ST data bus. This bus enables the Input dinN port Avalon-ST endofpacket signal. This signal Output dinN port Avalon-ST ready signal. This signal indicates Input dinN port Avalon-ST startofpacket signal.
PAGE 141
Color Space Conversion IP Cores 10 2015.05.04 UG-VIPSUITE Subscribe Send Feedback The Color Space Conversion IP cores transform video data between color spaces. The color spaces allow you to specify colors using three coordinate values. You can configure these IP cores to change conversion values at run time using an Avalon-MM slave interface. IP Cores Feature Color Space Converter (CSC) • Provides a flexible and efficient means to convert image data from one color space to another.
PAGE 142
10-2 UG-VIPSUITE 2015.05.04 Input and Output Data Types National Television System Committee (NTSC) systems or the Y'UV (luminance-bandwidthchrominance) color model for Phase Alternation Line (PAL) systems. Input and Output Data Types The inputs and outputs of the Color Space Conversion IP cores support signed or unsigned data and 4 to 20 bits per pixel per color plane. The IP cores also support minimum and maximum guard bands.
PAGE 143
UG-VIPSUITE 2015.05.04 Result of Output Data Type Conversion 10-3 If the channels are in sequence, din_0 is first, then din_1, and din_2. If the channels are in parallel, din_0 occupies the least significant bits of the word, din_1 the middle bits, and din_2 the most significant bits. For example, if there are 8 bits per sample and one of the predefined conversions inputs B’G’R’, din_0 carries B’ in bits 0–7, din_1 carries G’ in bits 8–15, and din_2 carries R’ in bits 16–23.
PAGE 144
10-4 UG-VIPSUITE 2015.05.04 Color Space Conversion Parameter Settings Color Space Conversion Parameter Settings Table 10-1: Color Space Converter Parameter Settings Parameter Value Description General Color plane configuration • Three color planes in sequence • Three color planes in parallel Specify whether to transmit the three color planes in sequence or in parallel. Input data type: Bits per pixel per color plane 4–20, Default = 8 Specify the number of input bits per pixel (per color plane).
PAGE 145
UG-VIPSUITE 2015.05.04 Color Space Conversion Parameter Settings Parameter Value 10-5 Description General Remove fraction bits by • Round values - Half Select the method of discarding fraction bits resulting from the calculation. up • Round values - Half even • Truncate values to integer Convert from signed to unsigned • Saturating to by minimum value at stage 4 • Replacing negative with absolute value Select the method of signed to unsigned conversion for the results.
PAGE 146
10-6 UG-VIPSUITE 2015.05.04 Color Space Conversion Parameter Settings Operands Coefficient and summands 12 fixed-point values A0, B0, C0, S0 A1, B1, C1, S1 A2, B2, C2, S2 Each coefficient or summand is represented by a white cell with a purple cell underneath. The value in the white cell is the desired value, and is editable. The value in the purple cell is the actual value, determined by the fixed-point type specified. The purple cells are not editable.
PAGE 147
UG-VIPSUITE 2015.05.04 Color Space Conversion Parameter Settings Parameter Value 10-7 Description General Maximum input frame height 32–4096, Default = 1080 Specify the maximum height of input images or video frames in pixels. Number of color planes 1–4, Default = 3 Specify the number of color planes. Color planes transmitted in parallel On or Off Turn on to transmit the color planes in parallel. Pixels in parallel 1, 2, or 4 Specify the number of pixels transmitted or received in parallel.
PAGE 148
10-8 UG-VIPSUITE 2015.05.04 Color Space Conversion Signals Parameter Value Description General Convert from signed to unsigned • Saturating to by minimum value at stage 4 • Replacing negative with absolute value Select the method of signed to unsigned conversion for the results. Operands Run-time control 32–4096, Default = 1920 Turn on to enable run-time control of the conversion values.
PAGE 149
UG-VIPSUITE 2015.05.04 Color Space Conversion Signals Signal Direction Description din_endofpacket Input din port Avalon-ST endofpacket signal. This signal marks the end of an Avalon-ST packet. din_ready Output din port Avalon-ST ready signal. This signal indicates Input din port Avalon-ST startofpacket signal. This signal din_startofpacket 10-9 when the IP core is ready to receive data. marks the start of an Avalon-ST packet. Input din port Avalon-ST valid signal.
PAGE 150
10-10 UG-VIPSUITE 2015.05.04 Color Space Conversion Control Registers Signal Direction Output control_byteenable Description control slave port Avalon-MM byteenable bus. This bus enables specific byte lane or lanes during transfers. Each bit in byteenable corresponds to a byte in writedata and readdata. • During writes, byteenable specifies which bytes are being written to; the slave ignores other bytes. • During reads, byteenable indicates which bytes the master is reading.
PAGE 151
UG-VIPSUITE 2015.05.04 Color Space Conversion Control Registers Address Register 2 Coefficient A0 3 Coefficient B0 4 Coefficient C0 5 Coefficient A1 6 Coefficient B1 7 Coefficient C1 8 Coefficient A2 9 Coefficient B2 10 Coefficient C2 11 Summand S0 12 Summand S1 13 Summand S2 10-11 Description The coefficient and summand registers use integer, signed 2’s complement numbers. Refer to Color Space Conversion on page 10-2.
PAGE 152
10-12 UG-VIPSUITE 2015.05.04 Color Space Conversion Control Registers Address Register 4 Coefficient A0 5 Coefficient B0 6 Coefficient C0 7 Coefficient A1 8 Coefficient B1 9 Coefficient C1 10 Coefficient A2 11 Coefficient B2 12 Coefficient C2 13 Summand S0 14 Summand S1 15 Summand S2 Altera Corporation Description The coefficient and summand registers use integer, signed 2’s complement numbers. Refer to Color Space Conversion on page 10-2.
PAGE 153
Control Synchronizer IP Core 11 2015.05.04 UG-VIPSUITE Subscribe Send Feedback The Control Synchronizer IP core synchronizes the configuration change of IP cores with an event in a video stream. For example, the IP core can synchronize the changing of a position of a video layer with the changing of the size of the layer.
PAGE 154
11-2 UG-VIPSUITE 2015.05.04 Using the Control Synchronizer IP Core Using the Control Synchronizer IP Core The example illustrates how the Control Synchronizer IP Core is set to trigger on the changing of the width field of control data packets.
PAGE 155
UG-VIPSUITE 2015.05.04 Using the Control Synchronizer IP Core 11-3 Figure 11-2: Changing Video Width Test Pattern Generator Avalon MM Frame Buffer Avalon MM Master Control Synchronizer Avalon MM Avalon MM Scaler Nios II CPU Red Line Indicates Control Data Packet and Video Data Packet Pair Number 5 (Width 320) Blue Line Indicates Control Data Packet and Video Data Packet Pair Number 1 (Width 640) Control Data Packet and Video Data Packet Pair Numbers 2, 3, and 4 are Stored in the Frame Buffer 3.
PAGE 156
11-4 UG-VIPSUITE 2015.05.
PAGE 157
UG-VIPSUITE 2015.05.04 Control Synchronizer Signals 11-5 Control Synchronizer Signals Table 11-2: Control Synchronizer Signals Signal Direction Description clock Input The main system clock. The IP core operates on the rising edge of this signal. reset Input The IP core asynchronously resets when this signal is high. You must deassert this signal synchronously to the rising edge of the clock signal. din_data Input din port Avalon-ST data bus.
PAGE 158
11-6 UG-VIPSUITE 2015.05.04 Control Synchronizer Control Registers Signal Direction Description slave_av_writedata Input slave port Avalon-MM writedata bus. The IP core uses these input lines for write transfers. status_update_int_w Output slave port Avalon-MM interrupt signal. Asserted to indicate that the interrupt registers of the IP core are updated; and the master must read them to determine what has occurred. master_av_address Output master port Avalon-MM address bus.
PAGE 159
UG-VIPSUITE 2015.05.04 Control Synchronizer Control Registers Address 3 Register Disable Trigger 11-7 Description • Setting this register to 1 disables the trigger condition of the control synchronizer. • Setting this register to 0 enables the trigger condition of the control synchronizer. When you turn on the Require trigger reset via control port parameter, this register value is automatically set to 1 every time the control synchronizer triggers.
PAGE 160
Deinterlacing IP Cores 12 2015.05.04 UG-VIPSUITE Subscribe Send Feedback The Deinterlacing IP cores provide deinterlacing algorithms. Interlaced video is commonly used in television standards such as phase alternation line (PAL) and national television system committee (NTSC), but progressive video is required by LCD displays and is often more useful for subsequent image processing functions. Additionally these cores also provide double -buffering or triple-buffering in external RAM.
PAGE 161
12-2 UG-VIPSUITE 2015.05.04 Deinterlacing Methods IP Cores Feature Broadcast Deinterlacer • Converts interlaced video to progressive video using high quality motion-adaptive algorithm.
PAGE 162
UG-VIPSUITE 2015.05.04 Bob with Scanline Duplication 12-3 Bob with Scanline Duplication The bob with scanline duplication algorithm is the simplest and cheapest in terms of logic. The bob with scanline duplication algorithm is the simplest and cheapest in terms of logic. Output frames are produced by simply repeating every line in the current field twice.
PAGE 163
12-4 UG-VIPSUITE 2015.05.04 Motion-Adaptive missing in the current field by calculating a function of other pixels in the current field and the three preceding fields as shown in the following sequence: 1. Pixels are collected from the current field and the three preceding it (the X denotes the location of the desired output pixel). Figure 12-1: Pixel Collection for the Motion-Adaptive Algorithm C-3 C-2 Current Field (C) C-1 X 2. These pixels are assembled into two 3×3 groups of pixels.
PAGE 164
UG-VIPSUITE 2015.05.04 Sobel-Based HQ Mode 12-5 The motion-adaptive algorithm requires the buffering of two frames of data before it can produce any output. The Deinterlacer always consumes the three first fields it receives at start up and after a change of resolution without producing any output. Note: The weave and motion-adaptive algorithms cannot handle fields of different sizes (for example, 244 lines for F0 and 243 lines for F1).
PAGE 165
12-6 UG-VIPSUITE 2015.05.04 Pass-Through Mode for Progressive Frames Pass-Through Mode for Progressive Frames In its default configuration, the Deinterlacing IP cores discard progressive frames. Change this behavior if you want a datapath compatible with both progressive and interlaced inputs and where run-time switching between the two types of input is allowed.
PAGE 166
UG-VIPSUITE 2015.05.04 Frame Buffering Types 12-7 Description Double-buffering • When you select double-buffering, external RAM uses two frame buffers. Input pixels flow through the input port and into one buffer while pixels are read from the other buffer, processed and output. • When both the input and output sides have finished processing a frame, the buffers swap roles so that the frame that the output can use the frame that you have just input.
PAGE 167
12-8 Frame Rate Conversion UG-VIPSUITE 2015.05.04 If the external memory in your system runs at a different clock rate to the Deinterlacing IP cores, you can turn on an option to use a separate clock for the Avalon-MM master interfaces and use the memory clock to drive these interfaces.
PAGE 168
UG-VIPSUITE 2015.05.04 Behavior When Unexpected Fields are Received 12-9 • Deinterlacer II processing 1080i60 input data • Phase 1: Read 2 lines = 1920 × 10 bits × 2 (YCbCr) × 2 × 1.0665 (inefficiency) = 81, 907.2 bits per line • Phase 2: Write 1 line, read 1 line = 1920 × 10 bits × 2 × 2 × 1.0665 = 81, 907.2 bits per line Read and write motion = 1920 × 8 bits × 2 × (one read and one write) = 30, 720 bits per line • Image data = Phase 1 + phase 2 accesses = 163, 814.
PAGE 169
12-10 UG-VIPSUITE 2015.05.04 Handling of Avalon-ST Video Control Packets When the bob algorithm is used and synchronization is done on a specific field (input frame rate = output frame rate), the field that is constantly unused is always discarded. The other field is used to build a progressive frame, unless it is dropped by the triple-buffering algorithm.
PAGE 170
UG-VIPSUITE 2015.05.04 Deinterlacing Parameter Settings Parameter Maximum image height Value 12-11 Description 32–2600, Default = 480 Specify the maximum progressive frame height in pixels. The maximum frame height is the default progressive height at start-up. Note: This IP core does not support interlaced streams where fields are not of the same size (for example, for NTSC, F0 has 244 lines, and F1 has 243 lines). Altera recommends that you use the Clipper IP cores to crop the extra line in F0.
PAGE 171
12-12 UG-VIPSUITE 2015.05.04 Deinterlacing Parameter Settings Parameter Value Description Frame buffering mode Specify whether to use external frame buffers. • No buffering • Double buffering • No buffering: data is piped directly from • Triple buffering input to output without using external with rate conversion memory. This is possible only with the bob method. • Double-buffering: routes data via a pair of buffers in external memory.
PAGE 172
UG-VIPSUITE 2015.05.04 Deinterlacing Parameter Settings Parameter 4:2:2 support for motion adaptive algorithm Value On or Off 12-13 Description Turn on to avoid color artefacts when processing 4:2:2 Y'CbCr data when you select Motion Adaptive deinterlacing method. You cannot turn on this parameter if you are not using either two channels in sequence or two channels in parallel. Note: Available only when you select Motion Adaptive as the deinter‐ lacing method.
PAGE 173
12-14 UG-VIPSUITE 2015.05.04 Deinterlacing Parameter Settings Parameter Maximum packet length Value 10–1024, Default = 10 Description Select the maximum packet length as a number of symbols. The minimum value is 10 because this is the size of an Avalon-ST control packet (header included). Extra samples are discarded if packets are larger than allowed. Note: You must select double or triplebuffering mode if you want to control the buffering of non-image data packets.
PAGE 174
UG-VIPSUITE 2015.05.04 Deinterlacing Parameter Settings Parameter Align read/write bursts with burst boundaries Value On or Off 12-15 Description Turn on to avoid initiating read and write bursts at a position that would cause the crossing of a memory row boundary. Note: Available only when you select Double buffering or Triple buffering with rate conversion.
PAGE 175
12-16 UG-VIPSUITE 2015.05.04 Deinterlacing Parameter Settings Parameter Run-time control Value On or Off Description Turn on to enable run-time control for the cadence detection and reverse pulldown. • Deinterlacer II : When turned off, the IP core always performs cadence detection and reverse pulldown if you turn on the Cadence detection and reverse pulldown parameter.
PAGE 176
UG-VIPSUITE 2015.05.04 Deinterlacing Signals Parameter Value 12-17 Description EDI read master FIFO depth 8–512, Default = 64 Select the FIFO depth of the edge-dependent interpolation (EDI) Avalon-MM read master interface. EDI read master FIFO burst target 2–256, Default = 32 Select the burst target for EDI Avalon-MM read master interface. MA read master FIFO depth 8–512, Default = 64 Select the FIFO depth of the motion-adaptive (MA) Avalon-MM read master interface.
PAGE 177
12-18 UG-VIPSUITE 2015.05.04 Deinterlacing Signals Signal Direction Description din_valid Input din port Avalon-ST valid signal. This signal identifies the cycles when the port must enter data. dout_data Output dout port Avalon-ST data bus. This bus enables the Output dout port Avalon-ST endofpacket signal. This signal dout_endofpacket dout_ready dout_startofpacket dout_valid transfer of pixel data out of the IP core. marks the end of an Avalon-ST packet.
PAGE 178
UG-VIPSUITE 2015.05.04 Deinterlacing Signals Signal Direction 12-19 Description ma_control_av_write Input ma_control_av_writedata Input read_master_N_av_address Output read_master_N port Avalon-MM address bus. This bus specifies a byte address in the Avalon-MM address space. read_master_N_av_burstcount Output read_master_N port Avalon-MM burstcount signal. This signal specifies the number of transfers in each burst. read_master_N_av_clock Input read_master_N port clock signal.
PAGE 179
12-20 UG-VIPSUITE 2015.05.04 Deinterlacing Signals Signal write_master_av_write write_master_av_writedata Direction Description Output write_master port Avalon-MM write signal. The IP core Output write_master port Avalon-MM writedata bus. These asserts this signal to indicate write requests from the master to the system interconnect fabric. output lines carry data for write transfers.
PAGE 180
UG-VIPSUITE 2015.05.04 Deinterlacing Signals Signal control_byteenable Direction Output 12-21 Description control slave port Avalon-MM byteenable bus. This bus enables specific byte lane or lanes during transfers. Each bit in byteenable corresponds to a byte in writedata and readdata. • During writes, byteenable specifies which bytes are being written to; the slave ignores other bytes. • During reads, byteenable indicates which bytes the master is reading.
PAGE 181
12-22 UG-VIPSUITE 2015.05.04 Deinterlacing Signals Signal Direction Description ma_read_master_waitrequest Input ma_read_master port Avalon-MM waitrequest signal. The system interconnect fabric asserts this signal to cause the master port to wait. motion_read_master_address Output motion_read_master port Avalon-MM address bus. Output motion_read_master port Avalon-MM read signal. The IP core asserts this signal to indicate read requests from the master to the system interconnect fabric.
PAGE 182
UG-VIPSUITE 2015.05.04 Deinterlacing Control Registers Signal Direction motion_write_master_ burstcount motion_write_master_ writedata motion_write_master_ waitrequest 12-23 Description Output motion_write_master port Avalon-MM burstcount Output motion_write_master port Avalon-MM writedata bus. Input motion_write_master port Avalon-MM waitrequest signal. This signal specifies the number of transfers in each burst. These output lines carry data for write transfers. signal.
PAGE 183
12-24 UG-VIPSUITE 2015.05.04 Deinterlacing Control Registers Table 12-9: Deinterlacer Control Register Map for Synchronizing the Input and Output Frame Rates The table below describes the control register map that synchronizes the input and output frame rates. The control data is read and registered when receiving the image data header that signals new frame. It can be safely updated during the processing of a frame.
PAGE 184
UG-VIPSUITE 2015.05.04 Deinterlacing Control Registers Address 4 Register Cadence detected 12-25 Description • Reading a 1 from bit 0, indicates that the Deinterlacer II IP core has detected a cadence and is performing reverse telecine. • Reading a 0 indicates otherwise. Table 12-11: Broadcast Deinterlacer Control Register Map The table below describes the Broadcast Deinterlacer IP core control register map for runtime control of the motion-adaptive algorithm.
PAGE 185
12-26 UG-VIPSUITE 2015.05.04 Deinterlacing Control Registers Address 4 Register 3:2 Cadence State (VOF State) RO/RW RO Description Indicates overall 3:2 cadence state. May be a decoder to determine whether the core is performing a weave with previous or incoming field. • 0 indicates that no 3:2 cadence is detected. • 2 indicates weave with previous field. • 3 indicates weave with incoming field.
PAGE 186
UG-VIPSUITE 2015.05.04 Deinterlacing Control Registers Address 12 Register Cadence Detect On RO/RW RW 12-27 Description • Setting the LSB of this register to 1 enables cadence detection. • Setting the LSB of this register to 0 disables cadence detection. • Cadence detection is disabled on reset. Range: 0–1 Power on value: 0 13 Video Threshold RW The most important register to tune the video over film features.
PAGE 187
12-28 UG-VIPSUITE 2015.05.04 Deinterlacing Control Registers Address 16 Register VOF Lock Delay RO/RW RW Description Specifies the number of fields elapsed after the core detects a cadence, but before reverse telecine begins. The delay allows for any video to drop out. If you set a value less than five, the core locks to cadence quicker but costs potential film artefacts.
PAGE 188
UG-VIPSUITE 2015.05.04 Deinterlacing Control Registers Address 22 Register History Minimum Value RO/RW RW 12-29 Description The cadence bias for a given pixel. Setting a lower value biases the pixels toward film, and setting a higher value biases the pixels toward video. The pixel SAD values are scaled according to the recent history that gives the frames an affinity for their historical state. Range: 0–3 Power on value: 3 23 History Maximum Value RW The cadence bias for a given pixel.
PAGE 189
12-30 UG-VIPSUITE 2015.05.04 Design Guidelines for Broadcast Deinterlacer IP Core Address 25 Register Motion Shift RO/RW RW Description Specifies the amount of raw motion (SAD) data that is right-shifted. Shifting is used to reduce sensitivity to noise when calculating motion (SAD) data for both bob and weave decisions and cadence detection. Note: It is very important to set this register correctly for good deinterlacing perform‐ ance.
PAGE 190
UG-VIPSUITE 2015.05.04 Design Guidelines for Broadcast Deinterlacer IP Core 12-31 Table 12-12: Suggested Register Settings For Altera UDX Reference Design The table below shows the suggested register settings for Altera’s High-Definition Video (UDX) reference design with 10-bit YCbCr video. Note: To ensure good quality, use these register settings after system reset. However, Altera recommends you to refine these settings, especially the motion shift register.
PAGE 191
12-32 UG-VIPSUITE 2015.05.04 Tuning Motion Shift Tuning Motion Shift To tune the motion shift register, follow these steps: 1. Enable motion visualization; set Visualize Motion Values register to 1. 2. Disable cadence detection to ensure pure deinterlacing function is being observed; set Cadence Detect On register to 0. 3. Feed the Broadcast Deinterlacer IP core with the sequence of interest, ideally one with static areas and areas in motion, such as a waving flag sequence.
PAGE 192
Frame Reader IP Core 13 2015.05.04 UG-VIPSUITE Subscribe Send Feedback The Frame Reader IP core reads video frames stored in external memory and outputs them as a video stream. You can configure the IP core to read multiple video frames using an Avalon-MM slave interface. The Frame Reader reads video frames stored in external memory and produces them using the Avalon-ST Video protocol. • Avalon-MM read master—reads data from an external memory.
PAGE 193
13-2 UG-VIPSUITE 2015.05.04 Frame Reader Output Pattern and Memory Organization width during compilation. Each word can only contain whole single-cycle color patterns. The words cannot contain partial single-cycle color patterns. Any bits of the word that cannot fit another whole single-cycle color pattern are not used.
PAGE 194
UG-VIPSUITE 2015.05.04 Frame Reader Parameter Settings 13-3 core, the Frame Reader IP core also has an interrupt that fires once per video data packet output, which is the frame completed interrupt. Frame Reader Parameter Settings Table 13-1: Frame Reader Parameter Settings Parameter Value Description Bits per pixel per color plane 4–20, Default = 8 Select the number of bits per pixel (per color plane).
PAGE 195
13-4 UG-VIPSUITE 2015.05.04 Frame Reader Signals Signal Direction Description Input dout port Avalon-ST ready signal. The downstream dout_startofpacket Output dout port Avalon-ST startofpacket signal. This signal marks the start of an Avalon-ST packet. dout_valid Output dout port Avalon-ST valid signal. The IP core asserts this dout_ready device asserts this signal when it is able to receive data. signal when it produces data. slave_av_address Input slave port Avalon-MM address bus.
PAGE 196
UG-VIPSUITE 2015.05.04 Frame Reader Control Registers Signal Direction master_av_waitrequest Input 13-5 Description master port Avalon-MM waitrequest signal. The system interconnect fabric asserts this signal to cause the master port to wait. Frame Reader Control Registers Table 13-3: Frame Reader Register Map The control data is read once at the start of each frame and is buffered inside the IP core, so the registers can be safely updated during the processing of a frame.
PAGE 197
13-6 UG-VIPSUITE 2015.05.04 Frame Reader Control Registers Address Register 11 Frame 1 Base Address 12 Frame 1 Words 13 Description The 32-bit base address of the frame. The number of words (reads from the master port) to read from memory for the frame. Frame 1 Single Cycle Color Patterns The number of single-cycle color patterns to read for the frame. 14 Frame 1 Reserved Reserved for future use.
PAGE 198
Frame Buffer IP Cores 14 2015.05.04 UG-VIPSUITE Subscribe Send Feedback The Frame Buffer IP cores buffer video frames into external RAM. IP Cores Feature Frame Buffer • Buffers progressive and interlaced video fields. • Supports double and triple buffering with a range of options for frame dropping and repeating • Supports 1 pixel per transmission. Frame Buffer II • Buffers progressive and interlaced video fields.
PAGE 199
14-2 UG-VIPSUITE 2015.05.04 Double Buffering Figure 14-1: Frame Buffer Block Diagram Avalon-ST Input (din) Memory Writer Memory Reader Avalon-MM Master (write_master) Avalon-ST Output (dout) Avalon-MM Master (read_master) Arbitration Logic DDR2 Double Buffering For double-buffering, the IP cores use two frame buffers in external RAM. • • • • The writer uses one buffer to store input pixels. The reader locks the second buffer that reads the output pixels from the memory.
PAGE 200
UG-VIPSUITE 2015.05.04 Locked Frame Rate Conversion 14-3 • The writer uses one buffer to store input pixels. • The reader locks the second buffer that reads the output pixels from the memory. • The third buffer is a spare buffer that allows the input and the output sides to swap buffers asynchro‐ nously. The spare buffer can be clean or dirty. • Considered clean if it contains a fresh frame that has not been sent.
PAGE 201
14-4 UG-VIPSUITE 2015.05.04 Color Format The user packets are never repeated and they are not dropped as long as memory space is sufficient. The control packets are not stored in memory. • The input control packets are processed and discarded by the writer. • The output control packets are regenerated by the reader. When a frame is dropped by the writer, it keeps the preceding non-image data packets and sends with the next frame that is not dropped.
PAGE 202
UG-VIPSUITE 2015.05.04 Frame Buffer Parameter Settings 14-5 Frame Buffer Parameter Settings Table 14-2: Frame Buffer Parameter Settings Parameter Value Description Maximum image width 32–2600, Default = 640 Specify the maximum frame width in pixels. Maximum image height 32–2600, Default = 480 Specify the maximum progressive frame height in pixels. In general, you should set this value to the full height of a progressive frame.
PAGE 203
14-6 UG-VIPSUITE 2015.05.04 Frame Buffer Parameter Settings Parameter Support for interlaced streams Value On or Off Description Turn on to support consistent dropping and repeating of fields in an interlaced video stream. Note: You must not turn on this parameter for double-buffering of an interlaced input stream on a field-by-field basis.
PAGE 204
UG-VIPSUITE 2015.05.04 Frame Buffer Parameter Settings Parameter Value Base address of frame buffers Any 32-bit value, Default = 0×00000000 14-7 Description Select a hexadecimal address of the frame buffers in external memory when buffering is used. The number of frame buffers and the total memory required at the specified base address is displayed under the base address.
PAGE 205
14-8 UG-VIPSUITE 2015.05.04 Frame Buffer Parameter Settings Parameter Value Description Write FIFO burst target 2–256, Default = 32 Select the burst target for the write-only Avalon-MM interface. Read FIFO depth Select the FIFO depth of the read-only Avalon-MM interface. 16–1024, Default = 64 Read FIFO burst target 2–256, Default = 32 Select the burst target for the read-only Avalon-MM interface.
PAGE 206
UG-VIPSUITE 2015.05.04 Frame Buffer Signals Parameter Value Description Run-time reader control On or Off Run-time control for the read interface. Avalon-MM master local ports width 16–256, Specify the width of the Avalon-MM ports used to access Default = 256 external memory. 14-9 Frame Buffer Signals Table 14-4: Common Signals for Frame Buffer IP Core The table lists the input and output signals for the Frame Buffer IP core.
PAGE 207
14-10 UG-VIPSUITE 2015.05.04 Frame Buffer Signals Signal Direction Description read_master_av_clock Input read_master port clock signal. The interface operates on the rising edge of the clock signal. read_master_av_reset Input read_master port reset signal. The interface asynchro‐ nously resets when this signal is high. You must deassert this signal synchronously to the rising edge of the clock signal. read_master_av_address Output read_master port Avalon-MM address bus.
PAGE 208
UG-VIPSUITE 2015.05.04 Frame Buffer Signals 14-11 Table 14-5: Reader Control Interface Signals for Frame Buffer IP Core These signals are present only if you turned on the control interface for the reader. Signal reader_control_av_ chipselect reader_control_av_readdata Direction Description Input reader control slave port Avalon-MM chipselect signal. The reader control port ignores all other signals unless you assert this signal. Output reader control slave port Avalon-MM readdata bus.
PAGE 209
14-12 UG-VIPSUITE 2015.05.04 Frame Buffer Signals Signal Direction Description mem_reset Input mem_master port reset signal. The interface asynchro‐ nously resets when this signal is high. You must deassert this signal synchronously to the rising edge of the clock signal. din_data Input din port Avalon-ST data bus. This bus enables the transfer of pixel data into the IP core. din_endofpacket Input din port Avalon-ST endofpacket signal. This signal marks the end of an Avalon-ST packet.
PAGE 210
UG-VIPSUITE 2015.05.04 Frame Buffer Control Registers Signal Direction 14-13 Description Output mem_master_wr port Avalon-MM address bus. This bus mem_master_wr_burstcount Output mem_master_wr port Avalon-MM burstcount signal. This signal specifies the number of transfers in each burst. mem_master_wr_waitrequest Input mem_master_wr port Avalon-MM waitrequest signal. mem_master_wr_address specifies a byte address in the Avalon-MM address space.
PAGE 211
14-14 UG-VIPSUITE 2015.05.04 Frame Buffer Control Registers Address Register 2 Frame Counter 3 Drop Counter 4 Controlled Rate Conversion 5 Input Frame Rate 6 Output Frame Rate Description Read-only register updated at the end of each frame processed by the writer. The counter is incremented if the frame is not dropped and passed to the reader. Read-only register updated at the end of each frame processed by the writer. The counter is incremented if the frame is dropped.
PAGE 212
UG-VIPSUITE 2015.05.04 Frame Buffer Control Registers 14-15 Table 14-10: Frame Buffer II Control Register Map for the Writer The table below describes the control register map for the writer component. Note: Addresses 4, 5, and 6 are optional and only visible on the control interface when you turn on Locked rate support in the parameter editor. Address Register Description 0 Control 1 Status Bit 0 of this register is the Status bit, all other bits are unused. 2 Interrupt Unused.
PAGE 213
14-16 UG-VIPSUITE 2015.05.04 Frame Buffer Control Registers Address 2 Register Interrupt Description Bits 2 and 1 are the interrupt status bits: • When bit 1 is asserted, the status update interrupt has triggered. • When bit 2 is asserted, the stable video interrupt has triggered. • The interrupts stay asserted until a 1 is written to these bits. 3 Frame Counter 4 Repeat Counter Altera Corporation Read-only register updated at the end of each frame processed by the reader.
PAGE 214
Gamma Corrector IP Core 15 2015.05.04 UG-VIPSUITE Subscribe Send Feedback The Gamma Corrector IP core corrects video streams for the physical properties of display devices. The Gamma Corrector IP core provides a look-up table (LUT) accessed through an Avalon-MM slave port. The gamma values can be entered in the LUT by external hardware using this interface. For example, the brightness displayed by a cathode-ray tube monitor has a nonlinear response to the voltage of a video signal.
PAGE 215
15-2 UG-VIPSUITE 2015.05.04 Gamma Corrector Signals Gamma Corrector Signals Table 15-2: Gamma Corrector Signals Signal Direction Description clock Input The main system clock. The IP core operates on the rising edge of this signal. reset Input The IP core asynchronously resets when this signal is high. You must deassert this signal synchronously to the rising edge of the clock signal. din_data Input din port Avalon-ST data bus.
PAGE 216
UG-VIPSUITE 2015.05.04 Gamma Corrector Control Registers Signal Direction 15-3 Description gamma_lut_av_write Input gamma_lut slave port Avalon-MM write signal. When you assert this signal, the reader control port accepts new data from the writedata bus. gamma_lut_av_writedata Input gamma_lutslave port Avalon-MM writedata bus. The IP core uses these input lines for write transfers. Gamma Corrector Control Registers The Gamma Corrector can have up to three Avalon-MM slave interfaces.
PAGE 217
15-4 UG-VIPSUITE 2015.05.04 Gamma Corrector Control Registers Address Register 2 to 2N +1 Gamma Look-Up Table where N is the number of bits per color plane. Description These registers contain a look-up table that is used to apply gamma correction to video data. An input intensity value of x is gamma corrected by replacing it with the contents of the (x +1)th entry in the look-up table. Changing the values of these registers has an immediate effect on the behavior of the IP core.
PAGE 218
Interlacer IP Core 16 2015.05.04 UG-VIPSUITE Subscribe Send Feedback The Interlacer IP core converts progressive video to interlaced video by dropping half the lines of incoming progressive frames. The Interlacer IP core generates an interlaced stream by dropping half the lines of each progressive input frame. The IP core drops odd and even lines in successive order to produce an alternating sequence of F0 and F1 fields. The output field rate is consequently equal to the input frame rate.
PAGE 219
16-2 UG-VIPSUITE 2015.05.04 Interlacer Parameter Settings Interlacer Parameter Settings Table 16-1: Interlacer Parameter Settings Parameter Value Description Maximum image width 32–2600, Default = 640 Specify the maximum frame width in pixels. The maximum frame width is the default width at start-up. Maximum image height 32–2600, Default = 480 Specify the maximum progressive frame height in pixels. The maximum frame height is the default progressive height at start-up.
PAGE 220
UG-VIPSUITE 2015.05.04 Interlacer Signals Signal Direction 16-3 Description reset Input The IP core asynchronously resets when this signal is high. You must deassert this signal synchronously to the rising edge of the clock signal. din_data Input din port Avalon-ST data bus. This bus enables the din_endofpacket Input din port Avalon-ST endofpacket signal. This signal marks the end of an Avalon-ST packet. din_ready Output din port Avalon-ST ready signal.
PAGE 221
16-4 UG-VIPSUITE 2015.05.04 Interlacer Control Registers Signal Direction Input control_av_writedata Description control slave port Avalon-MM writedata bus. The IP core uses these input lines for write transfers. Interlacer Control Registers Table 16-4: Interlacer Register Map The control interface is 8 bits wide but the Interlacer IP core only uses bit 0 of each addressable register.
PAGE 222
Scaler II IP Core 17 2015.05.04 UG-VIPSUITE Subscribe Send Feedback The Scaler II IP core resizes video streams, and supports nearest neighbor, bilinear, bicubic and polyphase scaling algorithms. The Scaler II algorithms provide a simple edge-adaptive scaling and 4:2:2 sampled video data. You can configure the Scaler II IP core to change the input resolution using control packets.
PAGE 223
17-2 UG-VIPSUITE 2015.05.04 Bilinear Algorithm For each output pixel, the nearest-neighbor method picks the value of the nearest input pixel to the correct input position. Formally, to find a value for an output pixel located at (i, j), the nearest-neighbor method picks the value of the nearest input pixel to ((i+0.5) win/wout, (j+0.5) hin/hout). The 0.
PAGE 224
UG-VIPSUITE 2015.05.04 Polyphase and Bicubic Algorithm 17-3 precision of each error variable is determined by the number of fraction bits chosen by the user, Bfh and Bfv, respectively. Their values can be calculated using the following equation: The sum is then weighted proportionally to these errors. Note: Because these values are measured from the top-left pixel, the weights for this pixel are one minus the error.
PAGE 225
17-4 UG-VIPSUITE 2015.05.04 Polyphase and Bicubic Algorithm Figure 17-1: Polyphase Mode Scaler Block Diagram The figure below shows the flow of data through an instance of the Scaler II in polyphase mode. Line Buffer Delay Line Buffer Delay Cv 0 Cv Nv Cv 1 ∑ Bit Narrowing Register Delay Register Delay Ch 0 Ch 1 Ch Nh ∑ Bit Narrowing Data from multiple lines of the input image are assembled into line buffers–one for each vertical tap.
PAGE 226
UG-VIPSUITE 2015.05.
PAGE 227
17-6 UG-VIPSUITE 2015.05.04 Polyphase Algorithmic Description Polyphase Algorithmic Description The algorithmic operations of the polyphase scaler can be modeled using a frame-based method. The filtering part of the polyphase scaler works by passing a windowed sinc function over the input data. • For up scaling, this function performs interpolation. • For down scaling, it acts as a low-pass filter to remove high-frequency data that would cause aliasing in the smaller output image.
PAGE 228
UG-VIPSUITE 2015.05.04 Choosing and Loading Coefficients 17-7 Figure 17-2: Lanczos 2 Function at Various Phases The figure below shows how a 2-lobe Lanczos-windowed sinc function (usually referred to as Lanczos 2) is sampled for a 4-tap vertical filter. Note: The two lobes refer to the number of times the function changes direction on each side of the central maxima, including the maxima itself. 1. 2 phase(0) phase( P v /2) phase( P v −1) 1 0. 8 0. 6 0. 4 0. 2 0 −0.
PAGE 229
17-8 UG-VIPSUITE 2015.05.04 Edge-Adaptive Scaling Algorithm Compile-time custom coefficients are loaded from a CSV file. One CSV file is specified for vertical coefficients and one for horizontal coefficients. For N taps and P phases, the file must contain N×P values. The values must be listed as N taps in order for phase 0, N taps for phase 1, up to the Nth tap of the Pth phase. You are not required to present these values with each phase on a separate line.
PAGE 230
UG-VIPSUITE 2015.05.04 Scaler II Parameter Settings 17-9 • The sharpening filter is primarily for downscale, but you may also use it with upscale. You may enable or disable this functionality at runtime. • The edge-adaptive sharpening filter attempts to detect blurred edge in the scaling video stream, and applies a sharpening filter where blurred edges are detected. • The areas that are not detected as blurred edges are left unaltered.
PAGE 231
17-10 UG-VIPSUITE 2015.05.04 Scaler II Parameter Settings Parameter Value Description No blanking in video On or Off Turn on if the input video does not contain vertical blanking at its point of conversion to the Avalon-ST video protocol. Scaling algorithm • • • • • Select the scaling algorithm. Enable post scaling sharpen On or Off Turn on to include a post-scaling edgeadaptive sharpening filter.
PAGE 232
UG-VIPSUITE 2015.05.04 Scaler II Parameter Settings Parameter Value 17-11 Description Default upper blur limit (per color plane) 0 to 2bits per symbol–1, Default = 15 Specify the default value for the blurred-edge upper threshold in edge-adaptive sharpening. This value will be the fixed edge threshold value if you do not turn on Enable run-time control of input/output frame size and edge/blur thresholds.
PAGE 233
17-12 UG-VIPSUITE 2015.05.04 Scaler II Signals Parameter Value Description Horizontal coefficient banks 1–32, Default = 1 Select the number of banks of horizontal filter coefficients for polyphase algorithms. Horizontal coefficient function • Lanczos_2 • Lanczos_3 • Custom Select the function used to generate the horizontal scaling coefficients. Select either one for the pre-defined Lanczos functions or choose Custom to use the coefficients saved in a custom coefficients file.
PAGE 234
UG-VIPSUITE 2015.05.04 Scaler II Signals Signal Direction 17-13 Description din_valid Input din port Avalon-ST valid signal. This signal identifies the cycles when the port must enter data. dout_data Output dout port Avalon-ST data bus. This bus enables the Output dout port Avalon-ST endofpacket signal. This signal dout_endofpacket dout_ready dout_startofpacket dout_valid transfer of pixel data out of the IP core. marks the end of an Avalon-ST packet.
PAGE 235
17-14 UG-VIPSUITE 2015.05.04 Scaler II Control Registers Signal Direction Description control_write Input control slave port Avalon-MM write signal. When you assert this signal, the control port accepts new data from the writedata bus. control_writedata Input slave port Avalon-MM writedata bus. The IP core uses these input lines for write transfers.
PAGE 236
UG-VIPSUITE 2015.05.04 Scaler II Control Registers Address Register 6 Lower Blur Threshold 7 Upper Blur Threshold 8 9 10 11 12 Horizontal Coefficient Write Bank Horizontal Coefficient Read Bank 17-15 Description Specifies the minimum difference between two pixels for a blurred edge to be detected between the pixels during post scaling edge-adaptive sharpening. To get the threshold used internally, this value is multiplied by the number of color planes per pixel.
PAGE 237
Video Switching IP Cores 18 2015.05.04 UG-VIPSUITE Subscribe Send Feedback The Video Switching IP cores allow the connection of up to twelve input video streams to twelve output video streams. You can configure the connections at run time through a control input. Table 18-1: Video Switching IP Cores IP Cores Feature Switch • Connects up to twelve input videos to 12 output videos. • Does not duplicate or combine streams.
PAGE 238
18-2 UG-VIPSUITE 2015.05.04 Mixer Layer Switching Mixer Layer Switching Layer switching is the ability to change the layer that a video stream is on, moving it in front of or behind the other video streams being mixed. You can use the Video Switching IP cores in conjunction with the Alpha Blending Mixer and Control Synchronizer IP cores to perform run-time configurable layer switching in the Alpha Blending Mixer IP core.
PAGE 239
UG-VIPSUITE 2015.05.04 Video Switching Parameter Settings 18-3 Video Switching Parameter Settings Table 18-2: Video Switching Parameter Settings Parameter Value Description Bits per pixel per color plane 4–20, Default = 8 Select the number of bits per pixel (per color plane). Number of color planes 1–3, Default = 3 Select the number of color planes. Color planes are in parallel On or Off • Turn on to set colors planes in parallel. • Turn off to set colors planes in sequence.
PAGE 240
18-4 UG-VIPSUITE 2015.05.04 Video Switching Signals Signal Direction Description Input din_N port Avalon-ST endofpacket signal. This signal Output din_N port Avalon-ST ready signal. The IP core asserts Input din_N port Avalon-ST startofpacket signal. This signal Input din_N port Avalon-ST valid signal. This signal identifies Output dout port Avalon-ST data bus. This bus enables the dout_N_endofpacket Output dout_N port Avalon-ST endofpacket signal.
PAGE 241
UG-VIPSUITE 2015.05.04 Video Switching Control Registers Signal Direction 18-5 Description Input alpha_out port Avalon-ST ready signal. The downstream alpha_out_N_startofpacket Output alpha_out port Avalon-ST startofpacket signal. This signal marks the start of an Avalon-ST packet. alpha_out_N_valid Output alpha_out port Avalon-ST valid signal. The IP core alpha_out_N_ready device asserts this signal when it is able to receive data. asserts this signal when it produces data.
PAGE 242
18-6 UG-VIPSUITE 2015.05.04 Video Switching Control Registers Table 18-6: Switch II Control Register Map The table below describes the control register map for Switch II IP core. Address 0 Register Control Description Bit 0 of this register is the Go bit. • Writing a 1 to bit 0 starts the IP core. • Writing a 0 to bit 0 stops the IP core. Bit 1 of this register is the interrupt enable bit. • Setting this bit to 1 enables the switching complete interrupt.
PAGE 243
Test Pattern Generator IP Cores 19 2015.05.04 UG-VIPSUITE Subscribe Send Feedback The Test Pattern Generator IP cores generate a video stream that displays either color bars for use as a test pattern or a constant color for use as a uniform background. You can use these IP cores during the design cycle to validate a video system without the possible throughput issues associated with a real video input.
PAGE 244
19-2 UG-VIPSUITE 2015.05.04 Test Pattern Figure 19-1: Color Bar Pattern The sequence to produce a static image runs through the eight possible on or off combinations of the three color components of the RGB color space starting with a 75% amplitude white.
PAGE 245
UG-VIPSUITE 2015.05.04 Generation of Avalon-ST Video Control Packets and Run-Time Control Color R'G'B' 19-3 Y'CbCr Green (16,180,16) (112,72,58) Magenta (180,16,180) (84,184,198) Red (180,16,16) (65,100,212) Blue (16,16,180) (35,212,114) Black (16,16,16) (16,128,128) The choice of a specific resolution and subsampling for the output leads to natural constraints on the test pattern.
PAGE 246
19-4 UG-VIPSUITE 2015.05.04 Test Pattern Generator Parameter Settings } } Test Pattern Generator Parameter Settings Table 19-2: Test Pattern Generator Parameter Settings Parameter Value Description Run-time control of image size On or Off Maximum image width 32-2600, Default = 640 Specify the maximum width of output in pixels. Maximum image height 32-2600, Default = 480 Specify the maximum height of output in pixels.
PAGE 247
UG-VIPSUITE 2015.05.04 Test Pattern Generator Parameter Settings 19-5 Table 19-3: Test Pattern Generator II Parameter Settings Parameter Value Description Run-time control of image size On or Off Maximum frame width 32-2600, Default = 640 Specify the maximum width of images/video frames in pixels. Maximum frame height 32-2600, Default = 480 Specify the maximum height of images/video frames in pixels. This value must be the height of the full progressive frame when producing interlaced data.
PAGE 248
19-6 UG-VIPSUITE 2015.05.04 Test Pattern Generator Signals Test Pattern Generator Signals Table 19-4: Test Pattern Generator Signals Signal Direction Description reset Input The IP core asynchronously resets when you assert this signal. You must deassert this signal synchronously to the rising edge of the clock signal. clock Input The main system clock. The IP core operates on the rising edge of this signal. control_av_address Input control slave port Avalon-MM address bus.
PAGE 249
UG-VIPSUITE 2015.05.04 Test Pattern Generator Signals Signal dout_startofpacket dout_valid Direction 19-7 Description Output dout port Avalon-ST startofpacket signal. This signal Output dout port Avalon-ST valid signal. The IP core asserts this marks the start of an Avalon-ST packet. signal when it produces data. Table 19-5: Test Pattern Generator II Signals Signal Direction Description reset Input The IP core asynchronously resets when you assert this signal.
PAGE 250
19-8 UG-VIPSUITE 2015.05.04 Test Pattern Generator Control Registers Signal Direction dout_data dout_endofpacket dout_ready dout_startofpacket dout_valid Description Output dout port Avalon-ST data bus. This bus enables the Output dout port Avalon-ST endofpacket signal. This signal Input dout port Avalon-ST ready signal. The downstream Output dout port Avalon-ST startofpacket signal. This signal Output dout port Avalon-ST valid signal.
PAGE 251
UG-VIPSUITE 2015.05.04 Test Pattern Generator Control Registers Address 4 Register 19-9 Description The value of the R (or Y) color sample when the test pattern is a uniform color background. R/Y Note: Available only when the IP core is configured to produce a uniform color background and run-time control interface is enabled. 5 The value of the G (or Cb) color sample when the test pattern is a uniform color background.
PAGE 252
19-10 UG-VIPSUITE 2015.05.04 Test Pattern Generator Control Registers Address 5 Register R/Y Description The value of the R (or Y) color sample when the test pattern is a uniform color background. Note: Available only when the IP core is configured to produce a uniform color background and run-time control interface is enabled. 6 G/Cb The value of the G (or Cb) color sample when the test pattern is a uniform color background.
PAGE 253
Trace System IP Core 20 2015.05.04 UG-VIPSUITE Subscribe Send Feedback The Trace System IP core is a debugging and monitoring component. The trace system collects data from various monitors, such as the Avalon-ST monitor, and passes it to System Console software on the attached debugging host. System Console software captures and visualizes the behavior of the attached system.
PAGE 254
20-2 UG-VIPSUITE 2015.05.04 Trace System Parameter Settings The IP core provides access to the control interfaces on the monitors. You can use these control ports to change the capture settings on the monitors; for example, to control the type of information captured by the monitors or to control the maximum data rate sent by the monitor. Note: Each type of monitor is different. Refer to the relevant documentation of the monitors for more information.
PAGE 255
UG-VIPSUITE 2015.05.04 Trace System Signals 20-3 Trace System Signals Table 20-2: Trace System Signals Signal clk_clk Direction Input Description All signals on the trace system are synchronous to this clock. Do not insert clock crossing between the monitor and the trace system components. You must drive the trace monitors’ clocks from the same source which drives this signal. reset_reset Output This signal is asserted when the IP core is being reset by the debugging host.
PAGE 256
20-4 UG-VIPSUITE 2015.05.04 Operating the Trace System from System Console Signal Direction Description Input capturen port Avalon-ST startofpacket signal. capturen_valid Input capturen port Avalon-ST valid signal. The IP core asserts this signal when it produces data. controln_address Output controln slave port Avalon-MM address bus. This Output controln slave port Avalon-MM burstcount signal. controln_byteenable Output controln slave port Avalon-MM byteenable bus.
PAGE 257
UG-VIPSUITE 2015.05.04 Loading the Project and Connecting to the Hardware 20-5 To start System Console, do one of the following steps: • Run system-console from the command line. • In Qsys, on the Tools menu, select Systems Debugging Tools > System Console. • In the Quartus II software, on the Tools menu, select Transceiver Toolkit. Note: Close the transceiver toolkit panes within System Console.
PAGE 258
20-6 UG-VIPSUITE 2015.05.04 Trace Within System Console • In the System Console window, on the File menu, select Load Design. Open the Quartus II Project File (.qpf) for your design. • From the System Console TCL shell, type the following command: [design_load
PAGE 259
UG-VIPSUITE 2015.05.04 TCL Shell Commands 20-7 Table 20-3: Functions of Trace Control Bar Icons The table lists the trace control bar, which lets you control the acquisition of data through the trace system. Icon Function Settings Displays the configuration dialog box again. Start Tells the trace system to start acquiring data. Data is displayed in the table view as soon as possible after it is acquired. Stop Stops acquiring data.
PAGE 260
20-8 UG-VIPSUITE 2015.05.04 TCL Shell Commands Command trace_get_monitor_info Arguments trace_read_monitor Function Returns a serialized array containing information about the specified monitor. You can use the array set command to convert this into a TCL array. Reads a 32-bit value from configuration space within the specified monitor.
PAGE 261
UG-VIPSUITE 2015.05.04 TCL Shell Commands Command trace_load Arguments 20-9 Function Loads a trace database from disk. This returns a new service path, which can be viewed as if it is a trace system. However, at this point, the start, stop and other commands will obviously not work on a file-based node. If you load a new trace database with the trace_load command, the trace user interface becomes visible if it was previously hidden.
PAGE 262
Avalon-ST Video Monitor IP Core 21 2015.05.04 UG-VIPSUITE Subscribe Send Feedback The Avalon-ST Video Monitor IP core is a debugging and monitoring component. The Avalon-ST Video Monitor IP core together with the associated software in System Console captures and visualizes the flow of video data in a system. You can inspect the video data flow at multiple levels of abstraction from the Avalon-ST video protocol level down to raw packet data level.
PAGE 263
21-2 UG-VIPSUITE 2015.05.04 Packet Visualization Note: System Console uses the sopcinfo file (written by Qsys) or the .sof (written by the Quartus II software) to discover the connections between the trace system and the monitors. If you instantiate and manually connect the trace system and the monitors using HDL, System Console will not detect them. Packet Visualization System Console's Trace Table View contains a tabular view for displaying the information the monitors send out.
PAGE 264
UG-VIPSUITE 2015.05.04 Monitor Settings Statistics Utilization 21-3 Description [Data transfer cycles / (Data transfer cycles + Not ready and valid cycles + Ready and not valid cycles + Not ready and not valid cycles + Inter packet valid cycles)] × 100 Note: Inter packet ready cycles are not included in the packet duration. A packet begins when a source is ready to send data. Monitor Settings The capture settings panel of the trace table provides convenient access to the monitor settings.
PAGE 265
21-4 UG-VIPSUITE 2015.05.04 Avalon-ST Video Monitor Signals Parameter Value Description Color planes transmitted in parallel On or Off • Turn on to transmit all the color planes at the same time in parallel. • Turn off to transmit all the color planes in series. Pixels in parallel 1, 2, or 4 Specify the number of pixels in parallel that the video pipeline is configured for. Note: You must specify this parameter value to 1 to capture video data frames.
PAGE 266
UG-VIPSUITE 2015.05.04 Avalon-ST Video Monitor Signals Signal Direction Description din_data Input din port Avalon-ST data bus. This bus enables the transfer of pixel data into the IP core. din_endofpacket Input din port Avalon-ST endofpacket signal. This signal marks the end of an Avalon-ST packet. din_ready Output din port Avalon-ST ready signal. This signal indicates Input din port Avalon-ST startofpacket signal.
PAGE 267
21-6 UG-VIPSUITE 2015.05.04 Avalon-ST Video Monitor Control Registers Signal Direction control_read controlreaddata Description Input control slave port Avalon-MM read signal. The IP core Output control slave port Avalon-MM readdata bus. These asserts this signal to indicate read requests from the master to the system interconnect fabric. input lines carry data for read transfers. Output control slave port Avalon-MM readdatavalid signal.
PAGE 268
UG-VIPSUITE 2015.05.04 Avalon-ST Video Monitor Control Registers Address 5 Register Control Avalon-ST Video Monitor IP Core Send Feedback 21-7 Description • Bits 15:0 control the linear feedback shift register (LFSR) mask for the pixel capture randomness function. The larger the mask, the less randomness is used to calculate the position of the next pixel to sample. • Bits 31:16 control the minimum gap between sampled pixels.
PAGE 269
Avalon-ST Video Verification IP Suite A 2015.05.04 UG-VIPSUITE Send Feedback Subscribe The Avalon-ST Video Verification IP Suite provides a set of SystemVerilog classes (the class library) that you can use to ensure that a video IP conforms to the Avalon-ST video standard. Figure A-1: Test Environment for the Avalon-ST Video Class Library The figure below shows the elements in the Avalon-ST Video Verification IP Suite.
PAGE 270
A-2 Avalon-ST Video Class Library UG-VIPSUITE 2015.05.04 Although the test environment in the example shows a simple example of using the class library, other test environments can conform to this test structure; with respect to the Verilog module-level connectivity and object/class-level connectivity. The class library uses the Avalon-ST source and sink BFM [1] and provides the following functionality: • Embodies the Avalon-ST Video standard to facilitate compliance testing.
PAGE 271
UG-VIPSUITE 2015.05.04 Avalon-ST Video Class Library A-3 Figure A-2: UML-Style Class Diagram The figure shows a unified modeling language (UML)-styled diagram of the class structure of the library and how these break down into individual files and packages. av _st _video _source _bfm _class .sv av _st _video _sink _bfm _class .
PAGE 272
A-4 UG-VIPSUITE 2015.05.04 Avalon-ST Video Class Library Table A-1: Class Description The table describes each of the classes in the av_st_video_classes package. Note: The classes listed do not contain information about the physical transport mechanism and the Avalon-ST Video protocol. To foster advanced verification techniques, Altera uses a high-level abstract view. Class class c_av_st_video_item Description The most fundamental of all the classes.
PAGE 273
UG-VIPSUITE 2015.05.04 Avalon-ST Video Class Library Class class c_av_st_video_control A-5 Description Parameterized class. Extends c_av_video_item. Comprises of width, height, and interlaced bits (the fields found in an Avalon-ST video control packet). It also contains data types and methods that control the addition of garbage beats that are used by other classes. The class provides methods to get and set the individual fields.
PAGE 274
A-6 UG-VIPSUITE 2015.05.04 Avalon-ST Video Class Library Class class c_av_st_video_source_bfm_ ’SOURCE Description Extends c_av_st_video_source_sink_base. Named according to the instance names of the Avalon-ST source and sink BFMs in the SystemVerilog netlist. This is because you must access the API functions in the Avalon-ST BFMs by directly calling them through the design hierarchy. Therefore, this hierarchy information is required in the Avalon-ST video source and sink classes.
PAGE 275
UG-VIPSUITE 2015.05.04 Running the Tests Class class c_av_st_video_file_io A-7 Description Parameterized class. Extends c_av_video_item. Comprises of width, height, and interlaced bits (the fields found in an Avalon-ST video control packet). It also contains data types and methods that control the addition of garbage beats that are used by other classes. The class provides methods to get and set the individual fields.
PAGE 276
A-8 UG-VIPSUITE 2015.05.04 Running the Tests a. Copy the verification files to a local directory and cd to the testbench directory. >cp $(QUARTUS_ROOTDIR)/../ip/altera/vip/verification $ALTERA_VIDEO_VERIFICATION >cd $ALTERA_VIDEO_VERIFICATION/testbench b. Start the Qsys system integration tool from the Quartus II software (tools > Qsys or through command line. G:\altera\14.0\quartus\sopc_builder\bin>qsys-edit c. Load the Qsys project. Double-click tb.qsys. d.
PAGE 277
UG-VIPSUITE 2015.05.04 Running the Tests A-9 Figure A-4: tb.v Netlist 2. Run the test by changing to the example video files test or example constrained random test directory and start the QuestaSim™ software. Note: You can also run this test with the ModelSim software but this test does not support the ModelSim-Altera Edition (AE) or ModelSim-Altera Starter Edition (ASE) softwares. ® • For example video files test: >cd $ALTERA_VIDEO_VERIFICATION/example_video_files >vsim –do run.
PAGE 278
A-10 UG-VIPSUITE 2015.05.04 Video File Reader Test To generate the .avi file, open a DOS command prompt from a Windows machine and run the following convertor utility: C:>raw2avi.exe vip_car_out.raw video.avi You can view the video.avi file with a media player. The media player shows a grayscale version of the source video file (vip_car_0.avi) that you can also play to see the full color video. You can view the full sequence from which the clip is taken in the vip_car.avi file.
PAGE 279
UG-VIPSUITE 2015.05.04 Video File Reader Test A-11 First, the test must define the numbers of bits per channel and channels per pixel, because most of the classes require this information. Next, the class packages are imported, the clock and reset defined, and the netlist itself instantiated with connections for clock and reset in place. Note: The BFM resets are all active high. If an active low reset is required, it may be necessary to invert the reset at the DUT input.
PAGE 280
A-12 UG-VIPSUITE 2015.05.04 Video File Reader Test and m_video_items_for_sink_bfm, each of type c_av_st_video_item. These shall be used to pass video items from the file reader into the source BFM and from the sink BFM to the file writer. At the end of this section, the file I/O class is used to declare the file reader and file writer objects. tb_test.sv—third section of the code.
PAGE 281
UG-VIPSUITE 2015.05.04 Example Test Environment A-13 do begin video_file_writer.wait_for_and_write_video_packet_to_file(); end while ( video_file_writer.get_video_packets_handled() < fields_read ); video_file_writer.close_file(); $finish; end The final section of the code is a three parallel blocks. The first and second blocks call the start methods for the source and sink video BFMs.
PAGE 282
A-14 UG-VIPSUITE 2015.05.04 Video Field Life Cycle Video Field Life Cycle Figure A-5: Video Field Life Cycle The figure below shows the life cycle of the video field.
PAGE 283
UG-VIPSUITE 2015.05.04 Constrained Random Test Stage A-15 Description Stage 3 • The video source BFM retrieves the data from its mailbox, recasts the data back into a c_av_st_video_data video object, and begins translating it into transactions for the Avalon-ST source BFM. • To indicate that a video packet is being sent, there is one transaction per pixel and an initial transaction with LSBs of 0×0 when using RGB24 data, 24-bit data buses, and parallel transmission.
PAGE 284
A-16 UG-VIPSUITE 2015.05.04 Code for Constrained Random Generation Figure A-6: Example of a Constrained Random Test Environment The figure below shows the constrained random test environment structure. tb_test.v (test environment) tb.
PAGE 285
UG-VIPSUITE 2015.05.04 Code for Scoreboards A-17 m_video_items_for_scoreboard.put(video_data_pkt2); end else if (r>34) begin video_control_pkt1.randomize(); m_video_items_for_src_bfm.put(video_control_pkt1); // Copy and send to scoreboard : video_control_pkt2 = new(); video_control_pkt2.copy(video_control_pkt1); m_video_items_for_scoreboard.put(video_control_pkt2); end else begin user_pkt1.set_max_length(33); user_pkt1.randomize() ; m_video_items_for_src_bfm.
PAGE 286
A-18 UG-VIPSUITE 2015.05.04 Code for to_grey Function begin // Get the reference item from the scoreboard mailbox : m_video_items_for_scoreboard.get(ref_pkt); // If the reference item is a video packet, then check // for the control & video packet response : if (ref_pkt.get_packet_type() == video_packet) begin m_video_items_for_sink_bfm.get(dut_pkt); if (dut_pkt.get_packet_type() != control_packet) $fatal(1,"SCOREBOARD ERROR”); m_video_items_for_sink_bfm.get(dut_pkt); if (dut_pkt.
PAGE 287
UG-VIPSUITE 2015.05.04 Complete Class Reference A-19 grey = new (); grey.packet_type = video_packet; do begin grey_pixel = new(); rgb_pixel = rgb.pop_pixel(); // Turn RGB into greyscale grey_value = ( red_factor green_factor blue_factor : * rgb_pixel.get_data(2) + * rgb_pixel.get_data(1) + * rgb_pixel.get_data(0)); grey_pixel.set_data(2, grey_value[15:8]); grey_pixel.set_data(1, grey_value[15:8]); grey_pixel.set_data(0, grey_value[15:8]); grey.push_pixel(grey_pixel); end while (rgb.
PAGE 288
A-20 UG-VIPSUITE 2015.05.04 c_av_st_video_control Method Call function t_packet_control get_append_garbage (); Description — function int get_garbage_probability (); — function void set_width (bit [15:0] w); — function void set_height (bit [15:0] h); — function void set_interlacing (bit [3:0] i); — function void set_append_garbage (t_packet_ control i); function void set_garbage_probability (int i); function string info(); Refer to append_garbage member.
PAGE 289
UG-VIPSUITE 2015.05.04 c_av_st_video_data A-21 c_av_st_video_data The declaration for the c_av_st_video_data class: class c_av_st_video_data#(parameter BITS_PER_CHANNEL = 8, CHANNELS_PER_PIXEL = 3) extends c_av_st_video_item; Table A-6: Method Calls for c_av_st_video_data Class Method Call Description function new(); Constructor function void copy (c_av_st_video_data c); Copies object c into this object. function bit compare (c_av_st_video_data r); Compares this instance to object r.
PAGE 290
A-22 UG-VIPSUITE 2015.05.04 c_av_st_video_file_io Table A-8: Method Calls for c_av_st_video_file_io Class Method Call function void set_send_control_packets(t_ packet_controls); Description If this method is used to set the send_ control_packet control to off, then one control packet is sent at the beginning of video data, but no further control packets are sent.
PAGE 291
UG-VIPSUITE 2015.05.
PAGE 292
A-24 UG-VIPSUITE 2015.05.04 c_av_st_video_file_io Method Call function void set_video_data_type(string s); Description Sets the fourcc[3] code associated with the raw video data. The following are the supported four character code (FOURCC) codes: • • • • • • function string get_video_data_type(); RGB32 IYU2 YUY2 Y410 A2R10GB10 Y210 Returns the FOURCC code (for example, RGB32) being used for the raw video data.
PAGE 293
UG-VIPSUITE 2015.05.04 c_av_st_video_file_io Method Call task read_video_packet(); task wait_for_and_write_video_packet_to_file() ; A-25 Description The main file reading method call. Binary data is read from the file and packed into pixel objects according to the settings of ycbr_ pixel_order and endianism. Pixel objects are packed into a video data object, with some pixels optionally added or discarded if late/ early EOP is being applied.
PAGE 294
A-26 UG-VIPSUITE 2015.05.04 c_av_st_video_item Member Description Int late_eop_probability = 20; — int user_packet_probability = 20; — int control_packet_probability = 20; — mailbox #(c_av_st_video_item) m_video_item_out = new(0); The mailbox is used to pass all packets in/out of the file i/o object.
PAGE 295
UG-VIPSUITE 2015.05.
PAGE 296
A-28 UG-VIPSUITE 2015.05.04 c_av_st_video_sink_bfm_’SINK Table A-13: Members of c_av_st_video_source_sink_base Class Member mailbox # (c_av_st_video_item) m_video_items= new(0); Description The Avalon-ST video standard allows you to send symbols in serial or parallel format. You can set this control to either format.
PAGE 297
UG-VIPSUITE 2015.05.04 c_av_st_video_source_bfm_’SOURCE A-29 Table A-14: Method Calls for c_av_st_video_sink_bfm_’SINK Class This class does not have additional members to those of the base class. Method Call function new(mailbox#(c_av_st_video_item)m_ vid); Description Constructor. The start method simply waits until the reset of the Avalon-ST sink BFM goes inactive, then calls the receive_video()task.
PAGE 298
A-30 UG-VIPSUITE 2015.05.04 c_av_st_video_user_packet Method Call Description The send_video() task waits until a video item is put into the mailbox, then it drives the Avalon-ST sink BFM's API accordingly. task send_video; The set_transaction_idles() call is used to set the valid signal in accordance with the probability settings in the base class. The mailbox object is categorized according to object type.
PAGE 299
UG-VIPSUITE 2015.05.04 c_pixel A-31 Table A-17: Members of c_av_st_video_user_packet Class Member rand bit[BITS_PER_CHANNEL*CHANNELS_PER_PIXEL1:0]data[$] Description User data is stored as a queue of words. rand bit[3:0] identifier; constraint c2 {identifier inside {[4:14]};} int max_length = 10; constraint c1 {data.
PAGE 300
A-32 Raw Video Data Format UG-VIPSUITE 2015.05.04 width (160) = 0 height (120) = 0 Choose output colorspace: 1.RGB 2.YCbCr 3.MONO 1 Choose output bps (8, 10) 8 Choose output interlacing: 1.progressive 2.interlaced F0 first 3.interlaced F1 first 1 Choose a number of frames to skip at the start of the sequence (use 0 to start t he decoding from the beginning) : 0 Choose the maximum number of frames to decode (use 0 to decode up to the end of the video) : 0 "raw" encoder created Decoding in progress.......
PAGE 301
UG-VIPSUITE 2015.05.04 Raw Video Data Format A-33 Figure A-7: Supported FOURCC Codes and Data Format The figure below shows an example of the data format required by the file I/O class for each of the supported FOURCC codes.
PAGE 302
Choosing the Correct Deinterlacer B 2015.05.04 UG-VIPSUITE Subscribe Send Feedback You should choose the right deinterlacer based on the quality of the output needed. The simple Bob deinterlacing option produces the lowest quality outputs; and the motion adaptive high quality (HQ) option produces the highest quality outputs. Figure B-1: Bob Deinterlacing Option The figure below shows an example output from Bob deinterlacing option.
PAGE 303
B-2 UG-VIPSUITE 2015.05.04 Choosing the Correct Deinterlacer Figure B-2: Motion Adaptive Deinterlacing Option The figure below shows an example output from Motion Adaptive deinterlacing option. To enable this option, select Motion Adaptive in the Deinterlacer or Deinterlacer II IP core parameter. If you are using the Deinterlacer IP core parameter editor, you need to select Triple buffering with rate conversion for the buffering mode.
PAGE 304
UG-VIPSUITE 2015.05.04 Cadence Detection and Reverse Pulldown in the Deinterlacer II IP Core B-3 With the moving Dial test sequence, the motion adaptive HQ mode improves the Bob interpolation further by operating on a 17×3 kernel of pixels. This allows much lower angles to be detected and interpo‐ lated, thus eliminating the staircasing effect almost completely. The area is 8,252 LUTs.
PAGE 305
B-4 UG-VIPSUITE 2015.05.04 Cadence Detection and Reverse Pulldown in the Deinterlacer II IP Core Figure B-6: 3:2 Detection and 2:2 Detection Comparison The figure below shows the comparison between 3:2 and 2:2 detection. 3 1 1 7 5 1 2 1 3 2 3 2 3 1 3 8 5 2 7 3 1 4 6 4 1 4 4 2 3 2 4 4 6 The 3:2 cadence detector tries to detect matches separated by four mismatches. When 3:2 cadence detector sees this pattern a couple of times, it locks.
PAGE 306
C Additional Information 2015.05.04 UG-VIPSUITE Subscribe Send Feedback Additional information about the document and Altera. Document Revision History Date May 2015 Version 2015.05.04 Changes • Edited the description of the Input (0-3) Enable registers for the Mixer II IP core. The 1-bit registers are changed to 2-bit registers: • Set to bit 0 of the registers to display input 0. • Set to bit 1 of the registers to enable consume mode.
PAGE 307
C-2 UG-VIPSUITE 2015.05.04 Document Revision History Date Version Changes • Edited the parameter settings information for the Mixer II IP core. • Added description for new parameter Pattern which enables you to select the pattern for the background layer. • Removed information about Color planes transmitted in parallel . This feature is now default and internally handled through the hardware TCL file. • Edited the parameter settings information for the Frame Buffer II IP core.
PAGE 308
UG-VIPSUITE 2015.05.04 Document Revision History C-3 Date Version Changes August 2014 14.0 • Added new IP cores: Clocked Video Output II, Clocked Video Input II, Color Space Converter II, Mixer II, Frame Buffer II, Switch II, and Test Pattern Generator II. • Revised the performance and resource data for different configura‐ tions using Arria V and Cyclone V devices. • Added information about IP catalog and removed information about MegaWizard Plug-In Manager.
PAGE 309
C-4 UG-VIPSUITE 2015.05.04 Document Revision History Date Version January 2013 12.1 • Added Deinterlacer II Sobel-Based HQ Mode information for the Deinterlacer II IP core. • Updated Table 1–17 to include latest Deinterlacer II IP core perform‐ ance figures for Cyclone IV and Stratix V devices. • Edited the description of the rst signal for the Clocked Video Output IP core.
PAGE 310
UG-VIPSUITE 2015.05.04 How to Contact Altera Date Version C-5 Changes November 2009 9.1 • Added new IP cores: Frame Reader, Control Synchronizer, and Switch. • The Frame Buffer IP core supports controlled frame dropping or repeating to keep the input and output frame rates locked together. The IP core also supports buffering of interlaced video streams. • The Clipper, Frame Buffer, and Color Plane Sequencer IP cores now support four channels in parallel.