User guide

11–10 Chapter 11: Clocked Video Output MegaCore Function
Functional Description
Video and Image Processing Suite January 2013 Altera Corporation
User Guide
The Clocked Video Output MegaCore function can take in the SOF signal from a
Clocked Video Input MegaCore function and align its own SOF to this signal. The
Clocked Video Output SOF signal can be set to any position within the outgoing
video frame. The registers used to configure the SOF signal are measured from the
rising edge of the F0 vertical sync. A start of frame is indicated by a rising edge on the
SOF signal (0 to 1). Figure 11–2 on page 11–3 shows an example configuration.
Figure 11–5 shows how the Clocked Video Output MegaCore function compares the
two SOF signals to determine how far apart they are.
The Clocked Video Output MegaCore function then repeats or removes that number
of samples and lines in the output video to align the two SOF signals. If the SOF
signals are separated by less than a threshold number of samples (the value of the
Vcoclk Divider register), the Clocked Video Output does not alter the output video.
If your PFD clock tracking has a delay associated with it, Altera recommends that
even if the
vcoclk_div signal is not being used, you must set the Vcoclk Divider
register to a threshold value (for example, 1). This stops the Clocked Video Output
MegaCore function from resyncing every time a delay in clock tracking causes the
SOF signals to drift out by a clock cycle.
The current distance between the SOF signals is stored internally and when either the
repeat registers or the remove registers read 0 then the locked interrupt triggers.
Figure 11–5. Aligning the Output Video to the Incoming SOF
sof
Repeat 3 lines
vid_sof
sof
cvo_sof
remove_lines
repeat_lines
5
3