User guide

Chapter 11: Clocked Video Output MegaCore Function 11–11
Functional Description
January 2013 Altera Corporation Video and Image Processing Suite
User Guide
Figure 11–6 shows an example of how to connect the Clocked Video Input and
Clocked Video Output MegaCore functions to a video PLL.
Underflow
Moving between flow controlled Avalon-ST Video and clocked video can cause
problems if the flow controlled video does not provide data at a rate fast enough to
satisfy the demands of the outgoing clocked video.
The Clocked Video Output MegaCore function contains a FIFO that, when set to a
large enough value, can accommodate any “burstiness” in the flow data, as long as
the output rate of the downstream Avalon-ST Video components is equal to or higher
than that of the outgoing clocked video.
If this is not the case, the FIFO underflows. If underflow occurs, the MegaCore
function continues to output video and re-syncs the
startofpacket , for the next
image packet, from the Avalon-ST Video interface with the start of the next frame.
The underflow can be detected by looking at bit 2 of the
Status register. This bit is
sticky and if an underflow occurs, stays at 1 until the bit is cleared by writing a 1 to it.
In addition to the underflow bit, the current level of the FIFO can be read from the
Used Words register.
Figure 11–6. Example System Connections
Divider
+
-
Charge
Pump
Phase
Detector
VCXO
Feedback
Divider
27 MHz
Video PLL
SDI
RX
Clocked
Video
Input
Clocked
Video
Output
SDI
TX
sof
sof_locked
vid_clkrefclk_div
FPGA