User guide

11–16 Chapter 11: Clocked Video Output MegaCore Function
Signals
Video and Image Processing Suite January 2013 Altera Corporation
User Guide
Signals
Table 11–7 lists the input and output signals for the Clocked Video Output MegaCore
function.
Table 11–7. Clocked Video Output Signals (Part 1 of 2)
Signal Direction Description
rst In
The MegaCore function asynchronously resets when you assert
rst . You must
deassert
rst synchronously to the rising edge of the is_clk signal. When the
video in and video out do not use the same clock, this signal is resynchronized to
the output clock to be used in the output clock domain.
vid_clk In Clocked video clock. All the video input signals are synchronous to this clock.
av_address In
control slave port Avalon-MM address bus. Specifies a word offset into the slave
address space.
(1)
av_read In
control slave port Avalon-MM read signal. When you assert this signal, the
control port drives new data onto the read data bus.
(1)
av_readdata Out
control slave port Avalon-MM readdata bus. These output lines are used for
read transfers.
(1)
av_waitrequest Out
control slave port Avalon-MM waitrequest bus. When this signal is asserted,
the
control port cannot accept new transactions.
(1)
av_write In
control slave port Avalon-MM write signal. When you assert this signal, the
control port accepts new data from the write data bus.
(1)
av_writedata In
control slave port Avalon-MM writedata bus. These input lines are used for
write transfers.
(1)
is_clk In
Clock signal for Avalon-ST ports
dout and control . The MegaCore function
operates on the rising edge of the
is_clk signal.
is_data In
dout port Avalon-ST data bus. This bus enables the transfer of pixel data into the
MegaCore function.
is_eop In
dout port Avalon-ST endofpacket signal. Assert this signal when the downstream
device is ending a frame.
is_ready Out
dout port Avalon-ST ready signal. This signal is asserted when the MegaCore
function is able to receive data.
is_sop In
dout port Avalon-ST startofpacket signal. Assert this signal when the
downstream device is starting a new frame.
is_valid In
dout port Avalon-ST valid signal. Assert this signal when the downstream device
outputs data.
sof In
Start of frame signal. A rising edge (0 to 1) indicates the start of the video frame as
configured by the SOF registers. Connecting this signal to a Clocked Video Input
MegaCore function allows the output video to be synchronized to this signal.
sof_locked Out Start of frame locked signal. When high the sof signal is valid and can be used.
status_update_int Out
control slave port Avalon-MM interrupt signal. When asserted the status registers
of the MegaCore function have been updated and the master must read them to
determine what has occurred.
(1)
underflow Out
Clocked video underflow signal. A signal corresponding to the underflow sticky bit
of the Status register synchronized to vid_clk . This signal is for information only
and no action is required if it is asserted.
(1)