User guide
Table Of Contents
- Contents
- 1. About This MegaCore Function Suite
- Release Information
- Device Family Support
- Features
- Design Example
- Performance and Resource Utilization
- 2D FIR Filter
- 2D Median Filter
- Alpha Blending Mixer
- Avalon-ST Video Monitor
- Chroma Resampler
- Clipper
- Clocked Video Input
- Clocked Video Output
- Color Plane Sequencer
- Color Space Converter
- Control Synchronizer
- Deinterlacer
- Deinterlacer II
- Frame Buffer
- Gamma Corrector
- Interlacer
- Scaler
- Scaler II
- Switch
- Test Pattern Generator
- Trace System
- 2. Getting Started with Altera IP Cores
- 3. Interfaces
- Interface Types
- Avalon-ST Video Protocol
- Avalon-MM Slave Interfaces
- Avalon-MM Master Interfaces
- Buffering of Non-Image Data Packets in Memory
- 4. 2D FIR Filter MegaCore Function
- 5. 2D Median Filter MegaCore Function
- 6. Alpha Blending MegaCore Function
- 7. Avalon-ST Video Monitor MegaCore Function
- 8. Chroma Resampler MegaCore Function
- 9. Clipper MegaCore Function
- 10. Clocked Video Input MegaCore Function
- 11. Clocked Video Output MegaCore Function
- 12. Color Plane Sequencer MegaCore Function
- 13. Color Space Converter MegaCore Function
- 14. Control Synchronizer MegaCore Function
- 15. Deinterlacer MegaCore Function
- Core Overview
- Functional Description
- Parameter Settings
- Signals
- Control Register Maps
- 16. Deinterlacer II MegaCore Function
- 17. Frame Reader MegaCore Function
- 18. Frame Buffer MegaCore Function
- 19. Gamma Corrector MegaCore Function
- 20. Interlacer MegaCore Function
- 21. Scaler MegaCore Function
- 22. Scaler II MegaCore Function
- 23. Switch MegaCore Function
- 24. Test Pattern Generator MegaCore Function
- 25. Trace System MegaCore Function
- A. Avalon-ST Video Verification IP Suite
- B. Choosing the Correct Deinterlacer
- Additional Information

Chapter 11: Clocked Video Output MegaCore Function 11–17
Signals
January 2013 Altera Corporation Video and Image Processing Suite
User Guide
vcoclk_div
Out
A divided down version of
vid_clk (vcoclk)
. Setting the
Vcoclk Divider
register to be the number of samples in a line produces a horizontal reference on
this signal that a PLL can use to synchronize its output clock.
vid_data
Out Clocked video data bus. This bus transfers video data into the MegaCore function.
vid_datavalid
Out
(Separate Synchronization mode Only.) Clocked video data valid signal. This signal
is asserted when an active picture sample of video data is present on
vid_data
.
vid_f
Out
(Separate Synchronization Mode Only.) Clocked video field signal. For interlaced
input, this signal distinguishes between field 0 and field 1. For progressive video,
this signal is unused.
vid_h
Out
(Separate Synchronization Mode Only.) Clocked video horizontal blanking signal.
This signal is asserted during the horizontal blanking period of the video stream.
vid_h_sync
Out
(Separate Synchronization Mode Only.) Clocked video horizontal synchronization
signal. This signal is asserted during the horizontal synchronization period of the
video stream.
vid_ln
Out
(Embedded Synchronization Mode Only.) Clocked video line number signal. Used
with the SDI MegaCore function to indicate the current line number when the
vid_trs
signal is asserted.
vid_mode_change
Out
Clocked video mode change signal. This signal is asserted on the cycle before a
mode change occurs.
vid_sof
Out
Start of frame signal. A rising edge (0 to 1) indicates the start of the video frame as
configured by the SOF registers.
vid_sof_locked
Out
Start of frame locked signal. When high the
vid_sof
signal is valid and can be
used.
vid_std
Out
Video standard bus. Can be connected to the
tx_std
signal of the SDI MegaCore
function (or any other interface) to set the
Standard
register.
vid_trs
Out
(Embedded Synchronization Mode Only.) Clocked video time reference signal (TRS)
signal. Used with the SDI MegaCore function to indicate a TRS, when asserted.
vid_v
Out
(Separate Synchronization Mode Only.) Clocked video vertical blanking signal. This
signal is asserted during the vertical blanking period of the video stream.
vid_v_sync
Out
(Separate Synchronization Mode Only.) Clocked video vertical synchronization
signal. This signal is asserted during the vertical synchronization period of the video
stream.
Note to Table 11–7:
(1) These ports are present only if you turn on Use control port.
Table 11–7. Clocked Video Output Signals (Part 2 of 2)
Signal Direction Description