User guide

1–2 Chapter 1: About This MegaCore Function Suite
Release Information
Video and Image Processing Suite January 2013 Altera Corporation
User Guide
Release Information
Table 1–1 provides information about this release of the Altera Video and Image
Processing Suite MegaCore functions.
f For more information about this release, refer to the MegaCore IP Library Release Notes
and Errata.
Device Family Support
Table 1–2 defines the device support levels for Altera IP cores.
Table 1–3 lists the level of support offered by the SDI MegaCore function for each
Altera device family.
Table 1–1. Video and Image Processing Suite Release Information
Item Description
Version 12.1 (All MegaCore functions)
Release Date December 2012
Ordering Code IPS-VIDEO (Video and Image Processing Suite)
Product IDs
00B3 (2D FIR Filter)
00B4 (2D Median Filter)
00B5 (Alpha Blending Mixer)
00D1 (Avalon-ST Video
Monitor)
00B1 (Chroma Resampler)
00C8 (Clipper)
00C4 (Clocked Video Input)
00C5 (Clocked Video Output)
00C9 (Color Plane Sequencer)
0003 (Color Space Converter)
00D0 (Control Synchronizer)
00B6 (Deinterlacer)
00EE (Deinterlacer II)
00B2 (Gamma Corrector)
00DC (Interlacer)
00B7 (Scaler)
00E9 (Scaler II)
00CF (Switch)
00CA (Test Pattern Generator)
00ED (Trace System)
Vendor ID(s) 6AF7
Table 1–2. Altera IP Core Device Support Levels
FPGA Device Families HardCopy Device Families
Preliminary support—The IP core is verified with
preliminary timing models for this device family. The IP core
meets all functional requirements, but might still be
undergoing timing analysis for the device family. It can be
used in production designs with caution.
HardCopy Companion—The IP core is verified with
preliminary timing models for the HardCopy companion
device. The IP core meets all functional requirements, but
might still be undergoing timing analysis for the HardCopy
device family. It can be used in production designs with
caution.
Final support—The IP core is verified with final timing
models for this device family. The IP core meets all
functional and timing requirements for the device family and
can be used in production designs.
HardCopy Compilation—The IP core is verified with final
timing models for the HardCopy device family. The IP core
meets all functional and timing requirements for the device
family and can be used in production designs.
Table 1–3. Device Family Support (Part 1 of 2)
Device Family Support
Arria
®
GX Final
Arria II GX Final
Arria II GZ Final