User guide
Table Of Contents
- Contents
- 1. About This MegaCore Function Suite
- Release Information
- Device Family Support
- Features
- Design Example
- Performance and Resource Utilization
- 2D FIR Filter
- 2D Median Filter
- Alpha Blending Mixer
- Avalon-ST Video Monitor
- Chroma Resampler
- Clipper
- Clocked Video Input
- Clocked Video Output
- Color Plane Sequencer
- Color Space Converter
- Control Synchronizer
- Deinterlacer
- Deinterlacer II
- Frame Buffer
- Gamma Corrector
- Interlacer
- Scaler
- Scaler II
- Switch
- Test Pattern Generator
- Trace System
- 2. Getting Started with Altera IP Cores
- 3. Interfaces
- Interface Types
- Avalon-ST Video Protocol
- Avalon-MM Slave Interfaces
- Avalon-MM Master Interfaces
- Buffering of Non-Image Data Packets in Memory
- 4. 2D FIR Filter MegaCore Function
- 5. 2D Median Filter MegaCore Function
- 6. Alpha Blending MegaCore Function
- 7. Avalon-ST Video Monitor MegaCore Function
- 8. Chroma Resampler MegaCore Function
- 9. Clipper MegaCore Function
- 10. Clocked Video Input MegaCore Function
- 11. Clocked Video Output MegaCore Function
- 12. Color Plane Sequencer MegaCore Function
- 13. Color Space Converter MegaCore Function
- 14. Control Synchronizer MegaCore Function
- 15. Deinterlacer MegaCore Function
- Core Overview
- Functional Description
- Parameter Settings
- Signals
- Control Register Maps
- 16. Deinterlacer II MegaCore Function
- 17. Frame Reader MegaCore Function
- 18. Frame Buffer MegaCore Function
- 19. Gamma Corrector MegaCore Function
- 20. Interlacer MegaCore Function
- 21. Scaler MegaCore Function
- 22. Scaler II MegaCore Function
- 23. Switch MegaCore Function
- 24. Test Pattern Generator MegaCore Function
- 25. Trace System MegaCore Function
- A. Avalon-ST Video Verification IP Suite
- B. Choosing the Correct Deinterlacer
- Additional Information

14–2 Chapter 14: Control Synchronizer MegaCore Function
Functional Description
Video and Image Processing Suite January 2013 Altera Corporation
User Guide
scaling ratio of 1:1 (no scaling). The Frame Buffer is configured to drop and repeat;
this makes it impossible to calculate when packets streamed into the Frame Buffer are
streamed out to the Scaler, which means that the Scaler cannot be configured in
advance of a certain video data packet. The Control Synchronizer solves this problem,
as described in the following scenario.
1. Set up the change of video width as shown in Figure 14–1.
2. The Test Pattern Generator has changed the size of its Video Data Packet and
Control Data Packet pairs to 320 width. It is not known when this change will
propagate through the Frame Buffer to the Scaler (Figure 14–2).
Figure 14–1. Change of Video Width
Figure 14–2. Changing Video Width
Test Pattern
Generator
Frame
Buffer
Control
Synchronizer
Scaler
Nios II CPU
CPU Writes to
Test Pattern
Generator,
changing frame width to 320
Red Line Indicates Control Data Packet and Video Data Packet Pair Number 4 (Width 640)
Blue Line Indicates Control Data Packet and Video Data Packet Pair Number 0 (Width 640)
Control Data packet and Video Data Packet Pair Numbers 1, 2 and 3 are Stored in the Frame Buffer
CPU Writes to Control
Synchronizer, Configures it to
Change Scaler Output Size to 320 Width
When a Change in Width is Detected
Avalon MM
Avalon MM
Avalon MM
Avalon MM
Master
Test Pattern
Generator
Frame
Buffer
Control
Synchronizer
Scaler
Nios II CPU
Red Line Indicates Control Data Packet and Video Data Packet Pair Number 5 (Width 320)
Blue Line Indicates Control Data Packet and Video Data Packet Pair Number 1 (Width 640)
Control Data Packet and Video Data Packet Pair Numbers 2, 3, and 4 are Stored in the Frame Buffer
Avalon MM
Avalon MM
Avalon MM
Avalon MM
Master