User guide
Table Of Contents
- Contents
- 1. About This MegaCore Function Suite
- Release Information
- Device Family Support
- Features
- Design Example
- Performance and Resource Utilization
- 2D FIR Filter
- 2D Median Filter
- Alpha Blending Mixer
- Avalon-ST Video Monitor
- Chroma Resampler
- Clipper
- Clocked Video Input
- Clocked Video Output
- Color Plane Sequencer
- Color Space Converter
- Control Synchronizer
- Deinterlacer
- Deinterlacer II
- Frame Buffer
- Gamma Corrector
- Interlacer
- Scaler
- Scaler II
- Switch
- Test Pattern Generator
- Trace System
- 2. Getting Started with Altera IP Cores
- 3. Interfaces
- Interface Types
- Avalon-ST Video Protocol
- Avalon-MM Slave Interfaces
- Avalon-MM Master Interfaces
- Buffering of Non-Image Data Packets in Memory
- 4. 2D FIR Filter MegaCore Function
- 5. 2D Median Filter MegaCore Function
- 6. Alpha Blending MegaCore Function
- 7. Avalon-ST Video Monitor MegaCore Function
- 8. Chroma Resampler MegaCore Function
- 9. Clipper MegaCore Function
- 10. Clocked Video Input MegaCore Function
- 11. Clocked Video Output MegaCore Function
- 12. Color Plane Sequencer MegaCore Function
- 13. Color Space Converter MegaCore Function
- 14. Control Synchronizer MegaCore Function
- 15. Deinterlacer MegaCore Function
- Core Overview
- Functional Description
- Parameter Settings
- Signals
- Control Register Maps
- 16. Deinterlacer II MegaCore Function
- 17. Frame Reader MegaCore Function
- 18. Frame Buffer MegaCore Function
- 19. Gamma Corrector MegaCore Function
- 20. Interlacer MegaCore Function
- 21. Scaler MegaCore Function
- 22. Scaler II MegaCore Function
- 23. Switch MegaCore Function
- 24. Test Pattern Generator MegaCore Function
- 25. Trace System MegaCore Function
- A. Avalon-ST Video Verification IP Suite
- B. Choosing the Correct Deinterlacer
- Additional Information
Chapter 14: Control Synchronizer MegaCore Function 14–3
Functional Description
January 2013 Altera Corporation Video and Image Processing Suite
User Guide
3. The Video Data Packet and Control Data Packet pair with changed width of 320
have propagated through the Frame Buffer. The Control Synchronizer has
detected the change and triggered a write to the Scaler. The Control Synchronizer
has stalled the video processing pipeline while it performs the write, as shown in
Figure 14–3.
4. The Scaler has been reconfigured to output width 320 frames. The Control
Synchronizer has resumed the video processing pipeline. At no point did the
Scaling ratio change from 1:1, as shown in Figure Figure 14–4.
Avalon-ST Video Protocol Parameters
You can customize the Control Synchronizer according to the parameters listed in
Table 14–1.
Figure 14–3. Test Pattern Generator Change
Figure 14–4. Reconfigured Scaler.
Test Pattern
Generator
Frame
Buffer
Control
Synchronizer
Scaler
Nios II CPU
Red Line Indicates Control Data Packet and Video Data Packet Pair Number 14 (Width 320)
Blue Line Indicates Control Data Packet and Video Data Packet Pair Number 5 (Width 320)
Light Blue Line Indicates Control Data Packet and Video Data Packet Pair Number 4 (Width 640)
Control Data Packet and Video Data Packet Pair Numbers 6 to 13 are Stored in the Frame Buffer
Control Synchronizer Writes the Data to the
Specified Addresses. This Configures the
Scaler to an Output Width of 320
Avalon MM
Avalon MM
Avalon MM
Avalon MM
Master
Test Pattern
Generator
Frame
Buffer
Control
Synchronizer
Scaler
Nios II CPU
Red Line Indicates Control Data Packet and Video Data Packet Pair Number 14 (Width 320)
Blue Line Indicates Control Data Packet and Video Data Packet Pair Number 5 (Width 320)
Control Data Packet and Video Data Packet Pair Numbers 6 to 13 are Stored in the Frame Buffer
Avalon MM
Avalon MM
Avalon MM
Avalon MM
Master
Table 14–1. Control Synchronizer Avalon-ST Video Protocol Parameters (Part 1 of 2)
Parameter Value
Frame Width Run-time controlled. Any valid value supported.
Frame Height Run-time controlled. Any valid value supported.