User guide

1–4 Chapter 1: About This MegaCore Function Suite
Design Example
Video and Image Processing Suite January 2013 Altera Corporation
User Guide
During control packet processing, the MegaCore functions might stall frequently and
read/write less than once per clock cycle. During data processing, the MegaCore
functions generally process one input/output per clock cycle. There are, however,
some stalling cycles. Typically, these are for internal calculations between rows of
image data and between frames/fields.
When stalled, the MegaCore function signals that it is not ready to receive or produce
data. The time spent in the stalled state varies between MegaCore functions and their
parameterizations. In general, it is a few cycles between rows and a few more between
frames.
If data is not available at the input when required, all of the MegaCore functions stall,
and thus do not output data. With the exceptions of the Deinterlacer and Frame Buffer
in double or triple-buffering mode, none of the MegaCore functions ever overlap the
processing of consecutive frames. The first sample of frame F + 1 is not input until
after the last sample of frame F has been output.
When an
endofpacket signal is received unexpectedly (early or late), the MegaCore
function recovers from the error and prepares itself for the next valid packet (control
or data).
1 For more information about the stalling, throughput, and error recovery of each
MegaCore function, refer to the “Stall Behavior and Error Recovery” section of the
respective MegaCore Function chapter in this user guide.
Design Example
A provided design example offers a starting point to quickly understand the Altera
video design methodology, enabling you to build full video processing systems on an
FPGA.
f For more information about this design example, refer to AN427: Video and Image
Processing Up Conversion Example Design.