User guide

14–6 Chapter 14: Control Synchronizer MegaCore Function
Signals
Video and Image Processing Suite January 2013 Altera Corporation
User Guide
din_valid In
din port Avalon-ST valid signal. This signal identifies the cycles
when the port must input data.
dout_data Out
dout port Avalon-ST data bus. This bus enables the transfer of pixel
data out of the MegaCore function.
dout_endofpacket Out
dout port Avalon-ST endofpacket signal. This signal marks the
end of an Avalon-ST packet.
dout_ready in
dout port Avalon-ST ready signal. The downstream device asserts
this signal when it is able to receive data.
dout_startofpacket Out
dout port Avalon-ST startofpacket signal. This signal marks
the start of an Avalon-ST packet.
dout_valid Out
dout port Avalon-ST valid signal. This signal is asserted when the
MegaCore function is outputs data.
slave_av_address In
slave port Avalon-MM address. Specifies a word offset into the slave
address space.
slave_av_read In
slave port Avalon-MM read signal. When you assert this signal, the
slave port drives new data onto the read data bus.
slave_av_readdata Out
slave port Avalon-MM readdata bus. These output lines are used
for read transfers.
slave_av_write In
slave port Avalon-MM write signal. When you assert this signal, the
gamma_lut port accepts new data from the writedata bus.
slave_av_writedata In
slave port Avalon-MM writedata bus. These input lines are used
for write transfers.
status_update_int_w Out
slave port Avalon-MM interrupt signal. When asserted the
interrupt registers of the MegaCore function have been updated and the master
must read them to determine what has occurred.
master_av_address Out
master port Avalon-MM address bus. Specifies a byte address in
the Avalon-MM address space.
master_av_writedata Out
master port Avalon-MM writedata bus. These output lines carry
data for write transfers.
master_av_write Out
master port Avalon-MM write signal. Asserted to indicate write
requests from the master to the system interconnect fabric.
master_av_waitrequest In
master port Avalon-MM waitrequest signal. The system interconnect fabric
asserts this signal to cause the master port to wait.
Table 14–4. Control Synchronizer Signals (Part 2 of 2)
Signal Direction Description