User guide
Table Of Contents
- Contents
- 1. About This MegaCore Function Suite
- Release Information
- Device Family Support
- Features
- Design Example
- Performance and Resource Utilization
- 2D FIR Filter
- 2D Median Filter
- Alpha Blending Mixer
- Avalon-ST Video Monitor
- Chroma Resampler
- Clipper
- Clocked Video Input
- Clocked Video Output
- Color Plane Sequencer
- Color Space Converter
- Control Synchronizer
- Deinterlacer
- Deinterlacer II
- Frame Buffer
- Gamma Corrector
- Interlacer
- Scaler
- Scaler II
- Switch
- Test Pattern Generator
- Trace System
- 2. Getting Started with Altera IP Cores
- 3. Interfaces
- Interface Types
- Avalon-ST Video Protocol
- Avalon-MM Slave Interfaces
- Avalon-MM Master Interfaces
- Buffering of Non-Image Data Packets in Memory
- 4. 2D FIR Filter MegaCore Function
- 5. 2D Median Filter MegaCore Function
- 6. Alpha Blending MegaCore Function
- 7. Avalon-ST Video Monitor MegaCore Function
- 8. Chroma Resampler MegaCore Function
- 9. Clipper MegaCore Function
- 10. Clocked Video Input MegaCore Function
- 11. Clocked Video Output MegaCore Function
- 12. Color Plane Sequencer MegaCore Function
- 13. Color Space Converter MegaCore Function
- 14. Control Synchronizer MegaCore Function
- 15. Deinterlacer MegaCore Function
- Core Overview
- Functional Description
- Parameter Settings
- Signals
- Control Register Maps
- 16. Deinterlacer II MegaCore Function
- 17. Frame Reader MegaCore Function
- 18. Frame Buffer MegaCore Function
- 19. Gamma Corrector MegaCore Function
- 20. Interlacer MegaCore Function
- 21. Scaler MegaCore Function
- 22. Scaler II MegaCore Function
- 23. Switch MegaCore Function
- 24. Test Pattern Generator MegaCore Function
- 25. Trace System MegaCore Function
- A. Avalon-ST Video Verification IP Suite
- B. Choosing the Correct Deinterlacer
- Additional Information

15–14 Chapter 15: Deinterlacer MegaCore Function
Signals
Video and Image Processing Suite January 2013 Altera Corporation
User Guide
read_master_N_av_address
Out
read_master_N
port Avalon-MM
address
bus. This bus
specifies a byte address in the Avalon-MM address space.
(1)
,
(2)
,
(3)
read_master_N_av_burstcount
Out
read_master_N
port Avalon-MM
burstcount
signal. This
signal specifies the number of transfers in each burst.
(1)
,
(2)
,
(3)
read_master_N_av_clock
In
read_master_N
port clock signal. The interface operates
on the rising edge of the clock signal.
(1)
,
(2)
,
(3)
,
(4)
read_master_N_av_read
Out
read_master_N
port Avalon-MM
read
signal. The
MegaCore function asserts this signal to indicate read
requests from the master to the system interconnect fabric.
(1)
,
(2)
,
(3)
read_master_N_av_readdata
In
read_master_N
port Avalon-MM
readdata
bus. These
input lines carry data for read transfers.
(1)
,
(2)
,
(3)
read_master_N_av_readdatavalid
In
read_master_N
port Avalon-MM
readdatavalid
signal.
The system interconnect fabric asserts this signal when the
requested read data has arrived.
(1)
,
(2)
,
(3)
read_master_N_av_reset
In
read_master_N
port reset signal.
The interface asynchronously resets when this signal is
high. You must deassert this signal synchronously to the
rising edge of the
clock
signal.
(1)
,
(2)
,
(3)
,
(4)
read_master_N_av_waitrequest
In
read_master_N
port Avalon-MM
waitrequest
signal.
The system interconnect fabric asserts this signal to cause
the master port to wait.
(1)
,
(2)
,
(3)
write_master_av_address
Out
write_master
port Avalon-MM
address
bus. This bus
specifies a byte address in the Avalon-MM address space.
(1)
,
(3)
write_master_av_burstcount
Out
write_master
port Avalon-MM
burstcount
signal. This
signal specifies the number of transfers in each burst.
(1)
,
(2)
,
(3)
write_master_av_clock
In
write_master
port clock signal. The interface operates on
the rising edge of the clock signal.
(1)
,
(3)
,
(4)
write_master_av_reset
In
write_master
port reset signal. The interface
asynchronously resets when this signal is high. You must
deassert this signal synchronously to the rising edge of the
clock
signal.
(1)
,
(3)
,
(4)
write_master_av_waitrequest
In
write_master
port Avalon-MM
waitrequest
signal. The
system interconnect fabric asserts this signal to cause the
master port to wait.
(1)
,
(3)
write_master_av_write
Out
write_master
port Avalon-MM
write
signal. The
MegaCore function asserts this signal to indicate write
requests from the master to the system interconnect fabric.
(1)
,
(3)
Table 15–4. Deinterlacer Signals (Part 3 of 4)
Signal Direction Description