User guide

Table Of Contents
15–14 Chapter 15: Deinterlacer MegaCore Function
Signals
Video and Image Processing Suite January 2013 Altera Corporation
User Guide
read_master_N_av_address
Out
read_master_N
port Avalon-MM
address
bus. This bus
specifies a byte address in the Avalon-MM address space.
(1)
,
(2)
,
(3)
read_master_N_av_burstcount
Out
read_master_N
port Avalon-MM
burstcount
signal. This
signal specifies the number of transfers in each burst.
(1)
,
(2)
,
(3)
read_master_N_av_clock
In
read_master_N
port clock signal. The interface operates
on the rising edge of the clock signal.
(1)
,
(2)
,
(3)
,
(4)
read_master_N_av_read
Out
read_master_N
port Avalon-MM
read
signal. The
MegaCore function asserts this signal to indicate read
requests from the master to the system interconnect fabric.
(1)
,
(2)
,
(3)
read_master_N_av_readdata
In
read_master_N
port Avalon-MM
readdata
bus. These
input lines carry data for read transfers.
(1)
,
(2)
,
(3)
read_master_N_av_readdatavalid
In
read_master_N
port Avalon-MM
readdatavalid
signal.
The system interconnect fabric asserts this signal when the
requested read data has arrived.
(1)
,
(2)
,
(3)
read_master_N_av_reset
In
read_master_N
port reset signal.
The interface asynchronously resets when this signal is
high. You must deassert this signal synchronously to the
rising edge of the
clock
signal.
(1)
,
(2)
,
(3)
,
(4)
read_master_N_av_waitrequest
In
read_master_N
port Avalon-MM
waitrequest
signal.
The system interconnect fabric asserts this signal to cause
the master port to wait.
(1)
,
(2)
,
(3)
write_master_av_address
Out
write_master
port Avalon-MM
address
bus. This bus
specifies a byte address in the Avalon-MM address space.
(1)
,
(3)
write_master_av_burstcount
Out
write_master
port Avalon-MM
burstcount
signal. This
signal specifies the number of transfers in each burst.
(1)
,
(2)
,
(3)
write_master_av_clock
In
write_master
port clock signal. The interface operates on
the rising edge of the clock signal.
(1)
,
(3)
,
(4)
write_master_av_reset
In
write_master
port reset signal. The interface
asynchronously resets when this signal is high. You must
deassert this signal synchronously to the rising edge of the
clock
signal.
(1)
,
(3)
,
(4)
write_master_av_waitrequest
In
write_master
port Avalon-MM
waitrequest
signal. The
system interconnect fabric asserts this signal to cause the
master port to wait.
(1)
,
(3)
write_master_av_write
Out
write_master
port Avalon-MM
write
signal. The
MegaCore function asserts this signal to indicate write
requests from the master to the system interconnect fabric.
(1)
,
(3)
Table 15–4. Deinterlacer Signals (Part 3 of 4)
Signal Direction Description