User guide

Table Of Contents
15–16 Chapter 15: Deinterlacer MegaCore Function
Control Register Maps
Video and Image Processing Suite January 2013 Altera Corporation
User Guide
Table 155 describes the control register map that synchronizes the input and output
frame rates. The control data is read and registered when receiving the image data
header that signals new frame. It can be safely updated during the processing of a
frame.
Table 15–6. Deinterlacer Control Register Map for Synchronizing the Input and Output Frame Rates
Address Register Description
0
Control
Bit 0 of this register is the
Go
bit, all other bits are unused. Setting this bit to 0 causes the
Deinterlacer MegaCore function to stop before control information is read and before
receiving and buffering the next frame. While stopped, the Deinterlacer may freeze the
output and repeat a static frame if triple-buffering is enabled. Refer to “Avalon-MM Slave
Interfaces” on page 3–17 for full details.
1
Status
Bit 0 of this register is the
Status
bit, all other bits are unused. Refer to “Avalon-MM
Slave Interfaces” on page 3–17 for full details.
2
Input frame
rate
Write-only register. An 8-bit integer value for the input frame rate This register cannot be
read.
(1)
3
Output frame
rate
Write-only register. An 8-bit integer value for the output frame rate. The register cannot be
read.
(1)
Note to Table 15–6:
(1) The behavior of the rate conversion algorithm is not directly affected by a particular choice of input and output rates but only by their ratio.
23.976 -> 29.970 is equivalent to 24 -> 30.