User guide
Table Of Contents
- Contents
- 1. About This MegaCore Function Suite
- Release Information
- Device Family Support
- Features
- Design Example
- Performance and Resource Utilization
- 2D FIR Filter
- 2D Median Filter
- Alpha Blending Mixer
- Avalon-ST Video Monitor
- Chroma Resampler
- Clipper
- Clocked Video Input
- Clocked Video Output
- Color Plane Sequencer
- Color Space Converter
- Control Synchronizer
- Deinterlacer
- Deinterlacer II
- Frame Buffer
- Gamma Corrector
- Interlacer
- Scaler
- Scaler II
- Switch
- Test Pattern Generator
- Trace System
- 2. Getting Started with Altera IP Cores
- 3. Interfaces
- Interface Types
- Avalon-ST Video Protocol
- Avalon-MM Slave Interfaces
- Avalon-MM Master Interfaces
- Buffering of Non-Image Data Packets in Memory
- 4. 2D FIR Filter MegaCore Function
- 5. 2D Median Filter MegaCore Function
- 6. Alpha Blending MegaCore Function
- 7. Avalon-ST Video Monitor MegaCore Function
- 8. Chroma Resampler MegaCore Function
- 9. Clipper MegaCore Function
- 10. Clocked Video Input MegaCore Function
- 11. Clocked Video Output MegaCore Function
- 12. Color Plane Sequencer MegaCore Function
- 13. Color Space Converter MegaCore Function
- 14. Control Synchronizer MegaCore Function
- 15. Deinterlacer MegaCore Function
- Core Overview
- Functional Description
- Parameter Settings
- Signals
- Control Register Maps
- 16. Deinterlacer II MegaCore Function
- 17. Frame Reader MegaCore Function
- 18. Frame Buffer MegaCore Function
- 19. Gamma Corrector MegaCore Function
- 20. Interlacer MegaCore Function
- 21. Scaler MegaCore Function
- 22. Scaler II MegaCore Function
- 23. Switch MegaCore Function
- 24. Test Pattern Generator MegaCore Function
- 25. Trace System MegaCore Function
- A. Avalon-ST Video Verification IP Suite
- B. Choosing the Correct Deinterlacer
- Additional Information

15–16 Chapter 15: Deinterlacer MegaCore Function
Control Register Maps
Video and Image Processing Suite January 2013 Altera Corporation
User Guide
Table 15–5 describes the control register map that synchronizes the input and output
frame rates. The control data is read and registered when receiving the image data
header that signals new frame. It can be safely updated during the processing of a
frame.
Table 15–6. Deinterlacer Control Register Map for Synchronizing the Input and Output Frame Rates
Address Register Description
0
Control
Bit 0 of this register is the
Go
bit, all other bits are unused. Setting this bit to 0 causes the
Deinterlacer MegaCore function to stop before control information is read and before
receiving and buffering the next frame. While stopped, the Deinterlacer may freeze the
output and repeat a static frame if triple-buffering is enabled. Refer to “Avalon-MM Slave
Interfaces” on page 3–17 for full details.
1
Status
Bit 0 of this register is the
Status
bit, all other bits are unused. Refer to “Avalon-MM
Slave Interfaces” on page 3–17 for full details.
2
Input frame
rate
Write-only register. An 8-bit integer value for the input frame rate This register cannot be
read.
(1)
3
Output frame
rate
Write-only register. An 8-bit integer value for the output frame rate. The register cannot be
read.
(1)
Note to Table 15–6:
(1) The behavior of the rate conversion algorithm is not directly affected by a particular choice of input and output rates but only by their ratio.
23.976 -> 29.970 is equivalent to 24 -> 30.