User guide
Table Of Contents
- Contents
- 1. About This MegaCore Function Suite
- Release Information
- Device Family Support
- Features
- Design Example
- Performance and Resource Utilization
- 2D FIR Filter
- 2D Median Filter
- Alpha Blending Mixer
- Avalon-ST Video Monitor
- Chroma Resampler
- Clipper
- Clocked Video Input
- Clocked Video Output
- Color Plane Sequencer
- Color Space Converter
- Control Synchronizer
- Deinterlacer
- Deinterlacer II
- Frame Buffer
- Gamma Corrector
- Interlacer
- Scaler
- Scaler II
- Switch
- Test Pattern Generator
- Trace System
- 2. Getting Started with Altera IP Cores
- 3. Interfaces
- Interface Types
- Avalon-ST Video Protocol
- Avalon-MM Slave Interfaces
- Avalon-MM Master Interfaces
- Buffering of Non-Image Data Packets in Memory
- 4. 2D FIR Filter MegaCore Function
- 5. 2D Median Filter MegaCore Function
- 6. Alpha Blending MegaCore Function
- 7. Avalon-ST Video Monitor MegaCore Function
- 8. Chroma Resampler MegaCore Function
- 9. Clipper MegaCore Function
- 10. Clocked Video Input MegaCore Function
- 11. Clocked Video Output MegaCore Function
- 12. Color Plane Sequencer MegaCore Function
- 13. Color Space Converter MegaCore Function
- 14. Control Synchronizer MegaCore Function
- 15. Deinterlacer MegaCore Function
- Core Overview
- Functional Description
- Parameter Settings
- Signals
- Control Register Maps
- 16. Deinterlacer II MegaCore Function
- 17. Frame Reader MegaCore Function
- 18. Frame Buffer MegaCore Function
- 19. Gamma Corrector MegaCore Function
- 20. Interlacer MegaCore Function
- 21. Scaler MegaCore Function
- 22. Scaler II MegaCore Function
- 23. Switch MegaCore Function
- 24. Test Pattern Generator MegaCore Function
- 25. Trace System MegaCore Function
- A. Avalon-ST Video Verification IP Suite
- B. Choosing the Correct Deinterlacer
- Additional Information

Chapter 16: Deinterlacer II MegaCore Function 16–7
Signals
January 2013 Altera Corporation Video and Image Processing Suite
User Guide
control_readdata
Out
control
slave port Avalon-MM
readdata
bus. These
output lines are used for read transfers.
(4)
control_readdatavalid
Out
control
slave port Avalon-MM
readdatavalid
bus. The
MegaCore function asserts this signal when the
readdata
bus contains valid data in response to the
read
signal.
(4)
control_waitrequest
Out
control
slave port Avalon-MM
waitrequest
signal.
(4)
control_byteenable
In
control
slave port Avalon-MM
byteenable
bus. This bus
enables specific byte lane or lanes during transfers. Each
bit in
byteenable
corresponds to a byte in
writedata
and
readdata
. During writes,
byteenable
specifies
which bytes are being written to; the slave ignores other
bytes. During reads,
byteenable
indicates which bytes
the master is reading. Slaves that simply return
readdata
with no side effects are free to ignore
byteenable
during
reads.
(4)
edi_read_master_address
Out
edi_read_master
port Avalon-MM
address
bus. This
bus specifies a byte address in the Avalon-MM address
space.
(1)
edi_read_master_read
Out
edi_read_master
port Avalon-MM
read
signal. The
MegaCore function asserts this signal to indicate read
requests from the master to the system interconnect
fabric.
(1)
edi_read_master_burstcount
Out
edi_read_master
port Avalon-MM
burstcount
signal.
This signal specifies the number of transfers in each
burst.
(1)
edi_read_master_readdata
In
edi_read_master
port Avalon-MM
readdata
bus. These
input lines carry data for read transfers.
(1)
edi_read_master_readdatavalid
In
edi_read_master
port Avalon-MM
readdatavalid
signal. The system interconnect fabric asserts this signal
when the requested read data has arrived.
(1)
edi_read_master_waitrequest
In
edi_read_master
port Avalon-MM
waitrequest
signal.
The system interconnect fabric asserts this signal to cause
the master port to wait.
(1)
ma_read_master_address
Out
ma_read_master
port Avalon-MM
address
bus. This bus
specifies a byte address in the Avalon-MM address
space.
(1)
ma_read_master_read
Out
ma_read_master
port Avalon-MM
read
signal. The
MegaCore function asserts this signal to indicate read
requests from the master to the system interconnect
fabric.
(1)
ma_read_master_burstcount
Out
ma_read_master
port Avalon-MM
burstcount
signal.
This signal specifies the number of transfers in each
burst.
(1)
ma_read_master_readdata
In
ma_read_master
port Avalon-MM
readdata
bus. These
input lines carry data for read transfers.
(1)
ma_read_master_readdatavalid
In
ma_read_master
port Avalon-MM
readdatavalid
signal. The system interconnect fabric asserts this signal
when the requested read data has arrived.
(1)
Table 16–3. Deinterlacer II Signals (Part 2 of 4)
Signal Direction Description