User guide
Table Of Contents
- Contents
- 1. About This MegaCore Function Suite
- Release Information
- Device Family Support
- Features
- Design Example
- Performance and Resource Utilization
- 2D FIR Filter
- 2D Median Filter
- Alpha Blending Mixer
- Avalon-ST Video Monitor
- Chroma Resampler
- Clipper
- Clocked Video Input
- Clocked Video Output
- Color Plane Sequencer
- Color Space Converter
- Control Synchronizer
- Deinterlacer
- Deinterlacer II
- Frame Buffer
- Gamma Corrector
- Interlacer
- Scaler
- Scaler II
- Switch
- Test Pattern Generator
- Trace System
- 2. Getting Started with Altera IP Cores
- 3. Interfaces
- Interface Types
- Avalon-ST Video Protocol
- Avalon-MM Slave Interfaces
- Avalon-MM Master Interfaces
- Buffering of Non-Image Data Packets in Memory
- 4. 2D FIR Filter MegaCore Function
- 5. 2D Median Filter MegaCore Function
- 6. Alpha Blending MegaCore Function
- 7. Avalon-ST Video Monitor MegaCore Function
- 8. Chroma Resampler MegaCore Function
- 9. Clipper MegaCore Function
- 10. Clocked Video Input MegaCore Function
- 11. Clocked Video Output MegaCore Function
- 12. Color Plane Sequencer MegaCore Function
- 13. Color Space Converter MegaCore Function
- 14. Control Synchronizer MegaCore Function
- 15. Deinterlacer MegaCore Function
- Core Overview
- Functional Description
- Parameter Settings
- Signals
- Control Register Maps
- 16. Deinterlacer II MegaCore Function
- 17. Frame Reader MegaCore Function
- 18. Frame Buffer MegaCore Function
- 19. Gamma Corrector MegaCore Function
- 20. Interlacer MegaCore Function
- 21. Scaler MegaCore Function
- 22. Scaler II MegaCore Function
- 23. Switch MegaCore Function
- 24. Test Pattern Generator MegaCore Function
- 25. Trace System MegaCore Function
- A. Avalon-ST Video Verification IP Suite
- B. Choosing the Correct Deinterlacer
- Additional Information

Chapter 16: Deinterlacer II MegaCore Function 16–9
Control Map Registers
January 2013 Altera Corporation Video and Image Processing Suite
User Guide
Control Map Registers
Table 16–4 describes the Deinterlacer II MegaCore function control register map. The
Deinterlacer II reads the control data once at the start of each frame and buffers the
data inside the MegaCore function. The registers may safely update during the
processing of a frame.
motion_write_master_waitrequest
In
motion_write_master
port Avalon-MM
waitrequest
signal.The system interconnect fabric asserts this signal to
cause the master port to wait.
(2)
Notes to Table 16–3:
(1) Two read master interfaces are used:
edi_read_master
and
ma_read_master
.
(2) When you select Motion Adaptive High Quality or Motion Adaptive, one additional read master (
motion_read_master
) and one additional
write master (
motion_write_master
) ports are used to read and update motion values.
(3) Additional
av_mm_clock
and
av_mm_reset
signals are available when you turn on Use separate clocks for the Avalon-MM master
interface(s).
(4) The signals associated with the
control
slave port are not present unless you enable Run-time control.
Table 16–3. Deinterlacer II Signals (Part 4 of 4)
Signal Direction Description
Table 16–4. Deinterlacer II Control Register Map for Run-Time Control of the Motion-Adaptive Algorithm
Address Register Description
0
Control
Bit 0 of this register is the
Go
bit, all other bits are unused. Setting this bit to 0 causes
the Deinterlacer II to stop after generating the current output frame.
1
Status
Bit 0 of this register is the
Status
bit, all other bits are unused. When this bit is set
to 0, the Deinterlacer II either gets disabled through the
Go
bit or waits to receive
video data.
2 Reserved This register is reserved for future use.
3
Cadence detect on
Setting bit 0 of this register to 1 enables cadence detection. Setting bit 0 of this
register to 0 disables cadence detection. Cadence detection is disabled on reset.
4
Cadence detected
Reading a 1 from bit 0, indicates that the Deinterlacer II has detected a cadence and
is performing reverse telecine. Reading a 0 indicates otherwise.