User guide
Table Of Contents
- Contents
- 1. About This MegaCore Function Suite
- Release Information
- Device Family Support
- Features
- Design Example
- Performance and Resource Utilization
- 2D FIR Filter
- 2D Median Filter
- Alpha Blending Mixer
- Avalon-ST Video Monitor
- Chroma Resampler
- Clipper
- Clocked Video Input
- Clocked Video Output
- Color Plane Sequencer
- Color Space Converter
- Control Synchronizer
- Deinterlacer
- Deinterlacer II
- Frame Buffer
- Gamma Corrector
- Interlacer
- Scaler
- Scaler II
- Switch
- Test Pattern Generator
- Trace System
- 2. Getting Started with Altera IP Cores
- 3. Interfaces
- Interface Types
- Avalon-ST Video Protocol
- Avalon-MM Slave Interfaces
- Avalon-MM Master Interfaces
- Buffering of Non-Image Data Packets in Memory
- 4. 2D FIR Filter MegaCore Function
- 5. 2D Median Filter MegaCore Function
- 6. Alpha Blending MegaCore Function
- 7. Avalon-ST Video Monitor MegaCore Function
- 8. Chroma Resampler MegaCore Function
- 9. Clipper MegaCore Function
- 10. Clocked Video Input MegaCore Function
- 11. Clocked Video Output MegaCore Function
- 12. Color Plane Sequencer MegaCore Function
- 13. Color Space Converter MegaCore Function
- 14. Control Synchronizer MegaCore Function
- 15. Deinterlacer MegaCore Function
- Core Overview
- Functional Description
- Parameter Settings
- Signals
- Control Register Maps
- 16. Deinterlacer II MegaCore Function
- 17. Frame Reader MegaCore Function
- 18. Frame Buffer MegaCore Function
- 19. Gamma Corrector MegaCore Function
- 20. Interlacer MegaCore Function
- 21. Scaler MegaCore Function
- 22. Scaler II MegaCore Function
- 23. Switch MegaCore Function
- 24. Test Pattern Generator MegaCore Function
- 25. Trace System MegaCore Function
- A. Avalon-ST Video Verification IP Suite
- B. Choosing the Correct Deinterlacer
- Additional Information

17–2 Chapter 17: Frame Reader MegaCore Function
Functional Description
Video and Image Processing Suite January 2013 Altera Corporation
User Guide
The raw data that comprises a video frame in external memory is stored as a set of
single-cycle color patterns. In memory, the single-cycle color patterns must be
organized into word-sized sections. Each of these word-sized sections must contain as
many whole samples as possible, with no partial single-cycle color patterns. Unused
bits are in the most significant portion of the word-sized sections. Single-cycle color
patterns in the least significant bits are output first. The frame is read with words at
the starting address first.
Figure 17–1 shows the output pattern and memory organization for a Frame Reader
MegaCore, which is configured for:
■ 8 bits per pixel per color plane
■ 3 color planes in parallel
■ Master port width 64
Other Frame Reader parameters affect only resources and performance, or both. For
more information, refer to Table 17–1.
The Avalon Slave control port allows the specification of up to two memory locations,
each containing a video frame. Switching between these memory locations is
performed with a single register. This allows the Frame Reader MegaCore function to
read a series of frames from different memory addresses without having to set
multiple registers within the period of a single frame. This feature is useful when
reading very small frames, and helps to simplify control timing. To aid the timing of
control instructions and to monitor the core, the Frame Reader MegaCore function
also has an interrupt that fires once per video data packet output, which is the “frame
completed” interrupt.
Figure 17–1. Frame Reader Output Pattern and Memory Organization
Current Field (C)
C - 1
C - 2
C - 3
X
28 292724 25 26
16 171512 13 14
453012
34 353330 31 32
22 232118 19 20
10 119678
11
10 7
8
9
6
5
12
13
14
4
30
Start
Address
64-Bit Word
Frame Reader
MegaCore
Avalon Memory Map
Read Master Port
Avalon
Streaming Output
Single Cycle Color
External Memory
8 Bits
8 Bits
8 Bits
Cycle 4
Cycle 3
Cycle 2
Cycle 1
Cycle 0
1
2