User guide

Chapter 17: Frame Reader MegaCore Function 17–5
Control Register Maps
January 2013 Altera Corporation Video and Image Processing Suite
User Guide
Control Register Maps
The width of each register of the frame reader is 32 bits. The control data is read once
at the start of each frame. The registers may be safely updated during the processing
of a frame. Table 17–4 describes the Frame Reader run-time control registers.
master_av_read Out
master port Avalon-MM read signal. Asserted to
indicate read requests from the master to the system interconnect
fabric.
master_av_readdata In
master port Avalon-MM readdata bus. These input
lines carry data for read transfers.
master_av_readdatavalid In
master port Avalon-MM readdatavalid signal. The
system interconnect fabric asserts this signal when the requested
read data has arrived.
master_av_waitrequest In
master port Avalon-MM waitrequest signal. The
system interconnect fabric asserts this signal to cause the master
port to wait.
master_av_reset In
master port reset signal. The interface asynchronously
resets when you assert this signal. You must deassert this signal
synchronously to the rising edge of the
clock signal.
master_av_clock In
master port The clock signal. The interface operates on
the rising edge of the clock signal.
Table 17–3. Frame Reader Signals (Part 2 of 2)
Signal Direction Description
Table 17–4. Frame Reader Register Map for Run-Time Control (Part 1 of 2)
Address Register Description
0
Control
Bit 0 of this register is the Go bit. Setting this bit to 1 causes the Frame Reader to start
outputting data. Bit 1 of the Control register is the interrupt enable. Setting bit 1 to 1,
enables the end of frame interrupt.
1
Status
Bit 0 of this register is the Status bit. All other bits are unused. Refer to “Avalon-MM
Slave Interfaces” on page 3–17 for full details.
2
Interrupt
Bit 1 of this register is the end of frame interrupt bit. All other bits are unused. Writing a 1
to bit 1 resets the end of frame interrupt.
3
Frame Select
This register selects between frame 0 and frame 1 for next output. Frame 0 is selected by
writing a 0 here, frame is selected by writing a 1 here.
4
Frame 0 Base
Address
The 32-bit base address of the frame.
5
Frame 0 Words The number of words (reads from the master port) to read from memory for the frame.
6
Frame 0 Single
Cycle Color
Patterns
The number of single-cycle color patterns to read for the frame.
7
Frame 0
Reserved
Reserved for future use.
8
Frame 0 Width The Width to be used for the control packet associated with frame 0.
9
Frame 0 Height The Height to be used for the control packet associated with frame 0.
10
Frame 0
Interlaced
The interlace nibble to be used for the control packet associated with frame 0.