User guide
Table Of Contents
- Contents
- 1. About This MegaCore Function Suite
- Release Information
- Device Family Support
- Features
- Design Example
- Performance and Resource Utilization
- 2D FIR Filter
- 2D Median Filter
- Alpha Blending Mixer
- Avalon-ST Video Monitor
- Chroma Resampler
- Clipper
- Clocked Video Input
- Clocked Video Output
- Color Plane Sequencer
- Color Space Converter
- Control Synchronizer
- Deinterlacer
- Deinterlacer II
- Frame Buffer
- Gamma Corrector
- Interlacer
- Scaler
- Scaler II
- Switch
- Test Pattern Generator
- Trace System
- 2. Getting Started with Altera IP Cores
- 3. Interfaces
- Interface Types
- Avalon-ST Video Protocol
- Avalon-MM Slave Interfaces
- Avalon-MM Master Interfaces
- Buffering of Non-Image Data Packets in Memory
- 4. 2D FIR Filter MegaCore Function
- 5. 2D Median Filter MegaCore Function
- 6. Alpha Blending MegaCore Function
- 7. Avalon-ST Video Monitor MegaCore Function
- 8. Chroma Resampler MegaCore Function
- 9. Clipper MegaCore Function
- 10. Clocked Video Input MegaCore Function
- 11. Clocked Video Output MegaCore Function
- 12. Color Plane Sequencer MegaCore Function
- 13. Color Space Converter MegaCore Function
- 14. Control Synchronizer MegaCore Function
- 15. Deinterlacer MegaCore Function
- Core Overview
- Functional Description
- Parameter Settings
- Signals
- Control Register Maps
- 16. Deinterlacer II MegaCore Function
- 17. Frame Reader MegaCore Function
- 18. Frame Buffer MegaCore Function
- 19. Gamma Corrector MegaCore Function
- 20. Interlacer MegaCore Function
- 21. Scaler MegaCore Function
- 22. Scaler II MegaCore Function
- 23. Switch MegaCore Function
- 24. Test Pattern Generator MegaCore Function
- 25. Trace System MegaCore Function
- A. Avalon-ST Video Verification IP Suite
- B. Choosing the Correct Deinterlacer
- Additional Information
17–6 Chapter 17: Frame Reader MegaCore Function
Control Register Maps
Video and Image Processing Suite January 2013 Altera Corporation
User Guide
11
Frame 1 Base
Address
The 32-bit base address of the frame.
12
Frame 1 Words
The number of words (reads from the master port) to read from memory for the frame.
13
Frame 1 Single
Cycle Color
Patterns
The number of single-cycle color patterns to read for the frame.
14
Frame 1
Reserved
Reserved for future use.
15
Frame 1 Width
The Width to be used for the control packet associated with the frame.
16
Frame 1 Height
The Height to be used for the control packet associated with the frame.
17
Frame 1
Interlaced
The interlace nibble to be used for the control packet associated with the frame.
Table 17–4. Frame Reader Register Map for Run-Time Control (Part 2 of 2)
Address Register Description