User guide

18–6 Chapter 18: Frame Buffer MegaCore Function
Signals
Video and Image Processing Suite January 2013 Altera Corporation
User Guide
Signals
Table 18–4 lists the input and output signals for the Frame Buffer MegaCore function.
Maximum packet length 10–1024
Specify the maximum packet length as a number of
symbols. The minimum value is 10 because this is the size
of an Avalon-ST control packet (header included). Extra
samples are discarded if packets are larger than allowed.
Use separate clocks for the Avalon-
MM master interfaces
On or Off
Turn on to add a separate clock signal for the Avalon-MM
master interfaces so that they can run at a different speed
to the Avalon-ST processing. This decouples the memory
speed from the speed of the data path and is sometimes
necessary to reach performance target.
External memory port width 16–256, Default = 64 Choose the width of the external memory port.
Write-only master interface FIFO
depth
16–1024,
Default = 64
Choose the FIFO depth of the write-only Avalon-MM
interface.
Write-only master interface burst
target
2–256, Default = 32
Choose the burst target for the write-only Avalon-MM
interface.
Read-only master interface FIFO
depth
16–1024,
Default = 64
Choose the FIFO depth of the read-only Avalon-MM
interface.
Read-only master interface burst
target
2–256, Default = 32
Choose the burst target for the read-only Avalon-MM
interface.
Base address of frame buffers
(4)
Any 32-bit value,
Default = 0x00000000
Choose a hexadecimal address for the frame buffers in
external memory.
Align read/write bursts with burst
boundaries
On or Off
Turn on to avoid initiating read and write bursts at a
position that would cause the crossing of a memory row
boundary.
Notes to Table 18–3:
(1) Locked frame rate conversion cannot be turned on until dropping and repeating are allowed.
(2) Locked frame rate conversion cannot be turned on if the run-time control interface for the writer component has not been enabled.
(3) The Maximum packet length option is not available when the Number of packets buffered per frame is set to 0.
(4) The number of frame buffers and the total memory required at the specified base address is displayed under the base address.
Table 18–3. Frame Buffer Parameter Settings (Part 2 of 2)
Parameter Value Description
Table 18–4. Frame Buffer Signals (Part 1 of 3)
Signal Direction Description
clock In
The main system clock. The MegaCore function operates on the
rising edge of the
clock signal.
reset In
The MegaCore function asynchronously resets when you assert
reset . You must deassert reset synchronously to the rising
edge of the
clock signal.
din_data In
din port Avalon-ST data bus. This bus enables the transfer of
pixel data into the MegaCore function.
din_endofpacket In
din port Avalon-ST endofpacket signal. This signal marks the
end of an Avalon-ST packet.
din_ready Out
din port Avalon-ST ready signal. This signal indicates when the
MegaCore function is ready to receive data.