User guide

18–8 Chapter 18: Frame Buffer MegaCore Function
Control Register Maps
Video and Image Processing Suite January 2013 Altera Corporation
User Guide
Control Register Maps
A run-time control can be attached either to the writer component or to the reader
component of the Frame Buffer MegaCore function but not to both. The width of each
register is 16 bits.
Table 18–5 describes the Frame Buffer MegaCore function control register map for the
writer component.
write_master_av_burstcount Out
write_master port Avalon-MM burstcount signal. Specifies
the number of transfers in each burst.
write_master_av_clock In
write_master port clock signal. The interface operates on the
rising edge of the clock signal.
(1)
write_master_av_reset In
write_master port reset signal. The interface resets
asynchronously when you assert this signal. You must deassert
this signal synchronously to the rising edge of the clock signal.
(1)
write_master_av_waitrequest In
write_master port Avalon-MM waitrequest signal. The
system interconnect fabric asserts this signal to cause the master
port to wait.
write_master_av_write Out
write_master port Avalon-MM write signal. Asserted to
indicate write requests from the master to the system interconnect
fabric.
write_master_av_writedata Out
write_master port Avalon-MM writedata bus. These output
lines carry data for write transfers.
writer_control_av_chipselect In
writer_control slave port Avalon-MM chipselect signal. The
writer_control port ignores all other signals unless you assert
this signal.
(3)
writer_control_av_readdata Out
writer_control slave port Avalon-MM readdata bus. These
output lines are used for read transfers.
(3)
writer_control_av_write In
writer_control slave port Avalon-MM write signal. When you
assert this signal, the
writer_control port accepts new data
from the
writedata bus.
(3)
writer_control_av_writedata In
writer_control slave port Avalon-MM writedata bus. These
input lines are used for write transfers.
(3)
Notes to Table 18–4:
(1) Additional clock and reset signals are available when you turn on Use separate clocks for the Avalon-MM master interfaces.
(2) These ports are present only if the control interface for the reader component has been enabled.
(3) These ports are present only if the control interface for the writer component has been enabled
Table 18–4. Frame Buffer Signals (Part 3 of 3)
Signal Direction Description
Table 18–5. Frame Buffer Control Register Map for the Writer Component (Part 1 of 2)
Address Register(s) Description
0
Control
Bit 0 of this register is the Go bit. Setting this bit to 1 causes the Frame Buffer MegaCore
function to stop the next time control information is read to start outputting data. Refer
to “Avalon-MM Slave Interfaces” on page 3–17 for full details.
1
Status
Bit 0 of this register is the Status bit, all other bits are unused. Refer to “Avalon-MM
Slave Interfaces” on page 3–17 for full details.