User guide
Table Of Contents
- Contents
- 1. About This MegaCore Function Suite
- Release Information
- Device Family Support
- Features
- Design Example
- Performance and Resource Utilization
- 2D FIR Filter
- 2D Median Filter
- Alpha Blending Mixer
- Avalon-ST Video Monitor
- Chroma Resampler
- Clipper
- Clocked Video Input
- Clocked Video Output
- Color Plane Sequencer
- Color Space Converter
- Control Synchronizer
- Deinterlacer
- Deinterlacer II
- Frame Buffer
- Gamma Corrector
- Interlacer
- Scaler
- Scaler II
- Switch
- Test Pattern Generator
- Trace System
- 2. Getting Started with Altera IP Cores
- 3. Interfaces
- Interface Types
- Avalon-ST Video Protocol
- Avalon-MM Slave Interfaces
- Avalon-MM Master Interfaces
- Buffering of Non-Image Data Packets in Memory
- 4. 2D FIR Filter MegaCore Function
- 5. 2D Median Filter MegaCore Function
- 6. Alpha Blending MegaCore Function
- 7. Avalon-ST Video Monitor MegaCore Function
- 8. Chroma Resampler MegaCore Function
- 9. Clipper MegaCore Function
- 10. Clocked Video Input MegaCore Function
- 11. Clocked Video Output MegaCore Function
- 12. Color Plane Sequencer MegaCore Function
- 13. Color Space Converter MegaCore Function
- 14. Control Synchronizer MegaCore Function
- 15. Deinterlacer MegaCore Function
- Core Overview
- Functional Description
- Parameter Settings
- Signals
- Control Register Maps
- 16. Deinterlacer II MegaCore Function
- 17. Frame Reader MegaCore Function
- 18. Frame Buffer MegaCore Function
- 19. Gamma Corrector MegaCore Function
- 20. Interlacer MegaCore Function
- 21. Scaler MegaCore Function
- 22. Scaler II MegaCore Function
- 23. Switch MegaCore Function
- 24. Test Pattern Generator MegaCore Function
- 25. Trace System MegaCore Function
- A. Avalon-ST Video Verification IP Suite
- B. Choosing the Correct Deinterlacer
- Additional Information

Chapter 18: Frame Buffer MegaCore Function 18–9
Control Register Maps
January 2013 Altera Corporation Video and Image Processing Suite
User Guide
Note to Table 18–5:
(1) Addresses 4, 5, and 6 are optional and only visible on the control interface when the “support lock frame rate conversion” GUI option is checked.
Table 18–6 describes the Frame Buffer MegaCore function control register map for the
reader component.
2
Frame Counter
Read-only register updated at the end of each frame processed by the writer. The
counter is incremented if the frame is not dropped and passed to the reader component.
3
Drop Counter
Read-only register updated at the end of each frame processed by the writer. The
counter is incremented if the frame is dropped.
4
Controlled Rate
Conversion
Bit 0 of this register determines whether dropping and repeating of frames or fields is
tightly controlled by the specified input and output frame rates. Setting this bit to 0,
switches off the controlled rate conversion and returns the triple-buffering algorithm to
a free regime where dropping and repeating is only determined by the status of the
spare buffer.
5
Input Frame Rate
Write-only register. A 16-bit integer value for the input frame rate. This register cannot
be read.
6
Output Frame Rate
Write-only register. A 16-bit integer value for the output frame rate. This register cannot
be read.
Table 18–5. Frame Buffer Control Register Map for the Writer Component (Part 2 of 2)
Address Register(s) Description
Table 18–6. Frame Buffer Control Register Map for the Reader Component
Address Register(s) Description
0
Control
Bit 0 of this register is the
Go
bit, all other bits are unused. Setting this bit to 0 causes the
reader component to stop the next time control information is updated. While stopped,
the Frame Buffer may continue to receive and drop frame at its input if frame dropping is
enabled. Refer to “Avalon-MM Slave Interfaces” on page 3–17 for full details.
1
Status
Bit 0 of this register is the
Status
bit, all other bits are unused. Refer to “Avalon-MM
Slave Interfaces” on page 3–17 for full details.
2
Frame Counter
Read-only register updated at the end of each frame processed by the reader. The counter
is incremented if the frame is not repeated.
3
Repeat Counter
Read-only register updated at the end of each frame processed by the reader. The counter
is incremented if the frame is about to be repeated.