User guide

Chapter 21: Scaler MegaCore Function 21–15
Control Register Maps
January 2013 Altera Corporation Video and Image Processing Suite
User Guide
Control Register Maps
Table 21–8 describes the Scaler MegaCore function control register map.
The Scaler reads the control data once at the start of each frame and buffers the data
inside the MegaCore function. The registers may be safely updated during the
processing of a frame, unless the frame is a coefficient bank.
The coefficient bank that is being read by the Scaler must not be written to unless the
core is in a stopped state. To change the contents of the coefficient bank while the
Scaler is in a running state, you must use multiple coefficient banks to allow an
inactive bank to be changed without affecting the frame currently being processed.
The Scaler control interface allows the programming of 1 to 6 banks of coefficients and
their phases. You can preprogram these coefficients and phases before any video is
processed. The preprogramming is useful for rapid switching of scaling ratios as you
only required to update 2 bank select registers plus any resolution changes.
If you require more than 6 bank configurations, then you can change the bank data
externally. Using 2 banks allows one to be used by the Scaler while the other is being
configured, and reduces the extra time required in-between frames to very few
additional cycles.
Note that all Scaler registers are write-only except at address 1.
Table 21–8. Scaler Control Register Map (Part 1 of 2)
Address Register Description
0
Control
Bit 0 of this register is the Go bit, all other bits are unused. Setting this bit
to 0, causes the Scaler to stop the next time that control information is
read. Refer to “Avalon-MM Slave Interfaces” on page 3–17 for full details.
1
Status
Bit 0 of this register is the Status bit, all other bits are unused. The
Scaler MegaCore function sets this address to 0 between frames. It is set
to 1 while the MegaCore function is processing data and cannot be
stopped. Refer to “Avalon-MM Slave Interfaces” on page 3–17 for full
details.
2
Output Width The width of the output frames in pixels.
(1)
3 Output Height The height of the output frames in pixels.
(1)
4
Horizontal Coefficient
Bank Write Address
Specifies which memory bank horizontal coefficient writes from the
Avalon-MM interface are made into.
5
Horizontal Coefficient
Bank Read Address
Specifies which memory bank is used for horizontal coefficient reads
during data processing.
6
Vertical Coefficient Bank
Write Address
Specifies which memory bank vertical coefficient writes from the Avalon-
MM interface are made into.
(2)
7
Vertical Coefficient Bank
Read Address
Specifies which memory bank is used for vertical coefficient reads during
data processing
8 to 7+N
h
Horizontal Tap Data
Specifies values for the horizontal coefficients at a particular phase. Write
these values first, then the
Horizontal Phase to commit the write.
8+N
h
Horizontal Phase
Specifies which phase the Horizontal Tap Data applies to. Writing to
this location, commits the writing of tap data. This write must be made
even if the phase value does not change between successive sets of tap
data.