User guide

22–8 Chapter 22: Scaler II MegaCore Function
Control Register Maps
Video and Image Processing Suite January 2013 Altera Corporation
User Guide
Control Register Maps
Table 22–4 describes the Scaler II MegaCore function control register map. The
run-time control register map for the Scaler II MegaCore function is altered and does
not match the register map of the Scaler MegaCore function.
1 The N
taps
is the number of horizontal or vertical filter taps, whichever is larger.
The Scaler II reads the control data once at the start of each frame and buffers the data
inside the MegaCore function. The registers may be safely updated during the
processing of a frame, unless the frame is a coefficient bank.
The coefficient bank that is being read by the Scaler II must not be written to unless
the core is in a stopped state. To change the contents of the coefficient bank while the
Scaler II is in a running state, you must use multiple coefficient banks to allow an
inactive bank to be changed without affecting the frame currently being processed.
The Scaler II allows for dynamic bus sizing on the slave interface. The slave interface
includes a 4-bit byte enable signal, and the width of the data on the slave interface is
32 bits.
f For more information about dynamic bus sizing, refer to the “Avalon-MM Slave
Addressing” section in Avalon Interface Specifications.
dout_startofpacket Out
dout port Avalon-ST startofpacket signal. This signal marks the start of
an Avalon-ST packet.
dout_valid Out
dout port Avalon-ST valid signal. This signal is asserted when the
MegaCore function outputs data.
Note to Table 22–3:
(1) These ports are not present if you turn off Enable run-time control of input/output frame size and select Bilinear for Scaling algorithm in the
parameter editor.
Table 22–3. Scaler II Signals (Part 2 of 2)
Signal Direction Description
Table 22–4. Scaler II Control Register Map (Part 1 of 2)
Address Register Description
0
Control
Bit 0 of this register is the Go bit, all other bits are unused. Setting this bit
to 0, causes the Scaler II to stop the next time that control information is
read.
Bit 1 enables the edge adaptive coefficient selection (set to 1 to enable
this feature). Bit 2 enables edge adaptive sharpening (set to 1 to enable
this feature).
1
Status
Bit 0 of this register is the Status bit, all other bits are unused. When this
bit is set to 09, the Scaler II sets this address to 0 between frames. It is
set to 1 while the MegaCore function is processing data and cannot be
stopped.
2
Interrupt
This bit is not used because the Scaler II does not generate any
interrupts.
3
Output Width The width of the output frames in pixels.