User guide
Table Of Contents
- Contents
- 1. About This MegaCore Function Suite
- Release Information
- Device Family Support
- Features
- Design Example
- Performance and Resource Utilization
- 2D FIR Filter
- 2D Median Filter
- Alpha Blending Mixer
- Avalon-ST Video Monitor
- Chroma Resampler
- Clipper
- Clocked Video Input
- Clocked Video Output
- Color Plane Sequencer
- Color Space Converter
- Control Synchronizer
- Deinterlacer
- Deinterlacer II
- Frame Buffer
- Gamma Corrector
- Interlacer
- Scaler
- Scaler II
- Switch
- Test Pattern Generator
- Trace System
- 2. Getting Started with Altera IP Cores
- 3. Interfaces
- Interface Types
- Avalon-ST Video Protocol
- Avalon-MM Slave Interfaces
- Avalon-MM Master Interfaces
- Buffering of Non-Image Data Packets in Memory
- 4. 2D FIR Filter MegaCore Function
- 5. 2D Median Filter MegaCore Function
- 6. Alpha Blending MegaCore Function
- 7. Avalon-ST Video Monitor MegaCore Function
- 8. Chroma Resampler MegaCore Function
- 9. Clipper MegaCore Function
- 10. Clocked Video Input MegaCore Function
- 11. Clocked Video Output MegaCore Function
- 12. Color Plane Sequencer MegaCore Function
- 13. Color Space Converter MegaCore Function
- 14. Control Synchronizer MegaCore Function
- 15. Deinterlacer MegaCore Function
- Core Overview
- Functional Description
- Parameter Settings
- Signals
- Control Register Maps
- 16. Deinterlacer II MegaCore Function
- 17. Frame Reader MegaCore Function
- 18. Frame Buffer MegaCore Function
- 19. Gamma Corrector MegaCore Function
- 20. Interlacer MegaCore Function
- 21. Scaler MegaCore Function
- 22. Scaler II MegaCore Function
- 23. Switch MegaCore Function
- 24. Test Pattern Generator MegaCore Function
- 25. Trace System MegaCore Function
- A. Avalon-ST Video Verification IP Suite
- B. Choosing the Correct Deinterlacer
- Additional Information

Chapter 23: Switch MegaCore Function 23–5
Control Register Map
January 2013 Altera Corporation Video and Image Processing Suite
User Guide
Control Register Map
Table 23–4 describes the Switch MegaCore function control register map.
dout_N_startofpacket
Out
dout_N
port Avalon-ST
startofpacket
signal. This signal marks the
start of an Avalon-ST packet.
dout_N_valid
Out
dout_N
port Avalon-ST
valid
signal. This signal is asserted when the
MegaCore function outputs data.
Note to Table 23–3:
(1) These ports are present only when Alpha Enabled is turned on in the parameter editor.
Table 23–3. Switch Signals (Part 2 of 2)
Signal Direction Description
Table 23–4. Switch Control Register Map
Address Register(s) Description
0
Control
Writing a 1 to bit 0, starts the MegaCore function, writing a 0 to bit 0 stops the
MegaCore function.
1
Status
Reading a 1 from bit 0, indicates that the MegaCore function is running (video
is flowing through it), reading a 0 indicates that it is stopped.
2
Output Switch
Writing a 1 to bit 0, indicates that the video output streams must be
synchronized and then the new values in the output control registers must be
loaded.
3
Dout0 Output Control
A one-hot value that selects which video input stream must propagate to this
output. For example, for a 3 input switch:
■ 3'b000 = no output
■ 3'b001 = din_0
■ 3'b010 = din_1
■ 3'b100 = din_2
4
Dout1 Output Control
As
Dout0 Output Control
but for output
dout1
.
... ... ...
15
Dout12 Output Control
As
Dout0 Output Control
but for output
dout12
.