User guide

25–2 Chapter 25: Trace System MegaCore Function
Parameter Settings
Video and Image Processing Suite January 2013 Altera Corporation
User Guide
Each trace monitor sends information about interesting events through its capture
interface. The trace system multiplexes these data streams together and, if the trace
systems is running, stores them into a FIFO buffer. The contents of this buffer are
streamed to the host using as much as the available trace bandwidth.
The amount of buffering required depends on the amount of jitter inserted by the link,
in most cases, the default value of 32Kbytes is sufficient.
1 The System Console uses the sopcinfo file written by Qsys to discover the connections
between the trace system and the monitors. If you instantiate and manually connect
the trace system and the monitors using HDL, the System Console will not detect
them.
Parameter Settings
Table 25–1 lists the Trace System MegaCore function parameters.
Signals
Table 25–2 lists the input and output signals for the Trace System MegaCore function.
Table 25–1. Trace System Parameter Settings
Parameter Value Description
Connection to
host
JTAG or USB,
Default = JTAG
Choose the type of connection to the host running the System Console.
Bit width of
capture
interface(s)
8, 16, 32, 64, 0r 128,
Default = 32
Choose the data bus width of the Avalon-ST interface sending the captured
information.
Number of
inputs
1+
Choose the number of trace monitors which will be connected to this trace
system.
Buffer size
8k, 16k, 32k, or 64k
Default = 32k
Choose the size of the jitter buffer in bytes.
Insert pipeline
stages
Boolean
Enable this option to insert the pipeline stages within the trace system.
Enabling this option gives a higher f
max
but uses more logic.
Table 25–2. Trace System Signals (Part 1 of 2)
Signal Direction Description
clk_clk In
All signals on the trace system are synchronous to this clock.
Do not insert clock crossing between the monitor and the trace system
components. You must drive the trace monitors’ clocks from the same
source which drives this signal.
reset_reset Out
This signal is asserted when the trace system is being reset by the debugging
host. Connect this signal to the reset inputs on the trace monitors.
Do not reset parts of the system being monitored with this signal because
this will interfere with functionality of the system.
usb_if_clk In
Clock provided by On-Board USB-Blaster II.
All
usb_if signals are synchronous to this clock; the trace system provides
clock crossing internally.