User guide

Table Of Contents
3–14 Chapter 3: Interfaces
Avalon-ST Video Protocol
Video and Image Processing Suite January 2013 Altera Corporation
User Guide
There are five signals types (ready, valid, data, startofpacket, and endofpacket)
associated with each port. The
din_ready
signal is an output from the MegaCore
function and indicates when the input port is ready to receive data. The
din_valid
and
din_data
signals are both inputs. The source connected to the input port sets
din_valid
to logic '1' when
din_data
has useful information that must be sampled.
din_startofpacket
is an input signal that is raised to indicate the start of a packet,
with
din_endofpacket
signaling the end of a packet.
The five output port signals have equivalent but opposite semantics.
The sequence of events shown in Figure 3–12 is:
1. Initially,
din_ready
is logic '0', indicating that the MegaCore function is not ready
to receive data on the next cycle. Many of the Video and Image Processing Suite
MegaCore functions are not ready for a few clock cycles in between rows of image
data or in between video frames.
1 For further details of each MegaCore function, refer to the “Functional
Description” section of the respective MegaCore Function chapter in this
user guide.
2. The MegaCore function sets
din_ready
to logic '1', indicating that the input port is
ready to receive data one clock cycle later. The number of clock cycles of delay
which must be applied to a ready signal is referred to as ready latency in the
Avalon Interface Specifications. All of the Avalon-ST interfaces that the Video and
Image Processing Suite uses have a ready latency of one clock cycle.
3. The source feeding the input port sets
din_valid
to logic '1' indicating that it is
sending data on the data port and sets
din_startofpacket
to logic '1' indicating
that the data is the first value of a new packet. The data is 0, indicating that the
packet is video data.
4. The source feeding the input port holds
din_valid
at logic '1' and drops
din_startofpacket
indicating that it is now sending the body of the packet. It puts
all three color values of the top left pixel of the frame on to
din_data
.
5. No data is transmitted for a cycle even though
din_ready
was logic '1' during the
previous clock cycle and therefore the input port is still asserting that it is ready for
data. This could be because the source has no data to transfer. For example, if the
source is a FIFO, it could have become empty.
6. Data transmission resumes on the input port:
din_valid
transitions to logic '1' and
the second pixel is transferred on
din_data
. Simultaneously, the MegaCore
function begins transferring data on the output port. The example MegaCore
function has an internal latency of three clock cycles so the first output is
transferred three cycles after being received. This output is the type identifier for a
video packet being passed along the datapath.
1 For guidelines about the latencies of each Video and Image Processing
MegaCore function, refer to refer to the “Latency” section of the respective
MegaCore Function chapter in this user guide.
7. The third pixel is input and the first processed pixel is output.
8. For the final sample of a frame, the source sets
din_endofpacket
to logic '1',
din_valid
to '1', and puts the bottom-right pixel of the frame on to
din_data
.