User guide

Chapter 7: Avalon-ST Video Monitor MegaCore Function 7–5
Control Register Map
January 2013 Altera Corporation Video and Image Processing Suite
User Guide
Control Register Map
Table 7–4 describes the Avalon-ST Video Monitor MegaCore function control register
map.
control_writedata In control slave port Avalon-MM writedata bus.
control_waitrequest Out control slave port Avalon-MM waitrequest signal.
Table 7–3. Avalon-ST Video Monitor Signals (Part 2 of 2)
Signal Direction Description
Table 7–4. Avalon-ST Video Monitor Control Register Map
Address Register(s) Description
0
Identity
Read only register—manufacturer and monitor identities.
Bits 11:0 are identities for the manufacturer, Altera = 0×6E
Bits 27:12 are identities for the monitor, Avalon-ST video monitor = 0×110
1
Configuration
Information
For use of the System Console only.
2
Configuration
Information
For use of the System Console only.
3
Configuration
Information
For use of the System Console only.
4
Control
Writing a 1 to bit 0 and bit 8 sends statistic counters.
Writing a 1 to bit 0 and bit 9 sends up to first 6 beats on the Avalon-ST data bus.
Writing a 0 to bit 0 disables both the statistics and beats.