User guide

Chapter 10: Clocked Video Input MegaCore Function 10–5
Functional Description
January 2013 Altera Corporation Video and Image Processing Suite
User Guide
If the MegaCore function has not yet determined the format of the incoming video, it
uses the values specified under the Avalon-ST Video Initial/Default Control Packet
section in the parameter editor.
After determining an aspect of the incoming videos format, the MegaCore function
enters the value in the respective register, sets the registers valid bit in the
Status
register, and triggers the respective interrupts.
Table 10–4 lists the sequence for a 1080i incoming video stream.
Interrupts
The Clocked Video Input MegaCore function outputs a single interrupt line which is
the
OR of the following internal interrupts:
■ The status update interrupt—Triggers when a change of resolution in the
incoming video is detected.
■ Stable video interrupt—Triggers when the incoming video is detected as stable
(has a consistent sample length in two of the last three lines) or unstable (if, for
example, the video cable is removed). The incoming video is always detected as
unstable when the
vid_locked signal is low.
Both interrupts can be independently enabled using bits [2:1] of the
Control register.
Their values can be read using bits [2:1] of the
Interrupt register and a write of 1 to
either of those bits clears the respective interrupt.
Generator Lock
Generator lock (Genlock) is the technique for locking the timing of video outputs to a
reference source. Sources that are locked to the same reference can be switched
between cleanly, on a frame boundary. The Genlock functionality is enabled using the
Control register.
Table 10–4. Resolution Detection Sequence for a 1080i Incoming Video Stream
Status Interrupt
Active
Sample
Count
F0
Active
Line
Count
F1
Active
Line
Count
Total
Sample
Count
F0 Total
Sample
Count
F1 Total
Sample
Count
Description
00000000000 000 0 00000Start of incoming video.
00000101000 000 1,920 0 0 2,200 0 0 End of first line of video.
00100101000 100 1,920 0 0 2,200 0 0
Stable bit set and interrupt fired
—Two of last three lines had
the same sample count.
00100111000 100 1,920 540 0 2,200 563 0 End of first field of video.
00110111000 100 1,920 540 0 2,200 563 0
Interlaced bit set—Start of
second field of video.
00111111000 100 1,920 540 540 2,200 563 562 End of second field of video.
10111111000 110 1,920 540 540 2,200 563 562
Resolution valid bit set and
interrupt fired.