User guide
Table Of Contents
- Contents
- 1. About This MegaCore Function Suite
- Release Information
- Device Family Support
- Features
- Design Example
- Performance and Resource Utilization
- 2D FIR Filter
- 2D Median Filter
- Alpha Blending Mixer
- Avalon-ST Video Monitor
- Chroma Resampler
- Clipper
- Clocked Video Input
- Clocked Video Output
- Color Plane Sequencer
- Color Space Converter
- Control Synchronizer
- Deinterlacer
- Deinterlacer II
- Frame Buffer
- Gamma Corrector
- Interlacer
- Scaler
- Scaler II
- Switch
- Test Pattern Generator
- Trace System
- 2. Getting Started with Altera IP Cores
- 3. Interfaces
- Interface Types
- Avalon-ST Video Protocol
- Avalon-MM Slave Interfaces
- Avalon-MM Master Interfaces
- Buffering of Non-Image Data Packets in Memory
- 4. 2D FIR Filter MegaCore Function
- 5. 2D Median Filter MegaCore Function
- 6. Alpha Blending MegaCore Function
- 7. Avalon-ST Video Monitor MegaCore Function
- 8. Chroma Resampler MegaCore Function
- 9. Clipper MegaCore Function
- 10. Clocked Video Input MegaCore Function
- 11. Clocked Video Output MegaCore Function
- 12. Color Plane Sequencer MegaCore Function
- 13. Color Space Converter MegaCore Function
- 14. Control Synchronizer MegaCore Function
- 15. Deinterlacer MegaCore Function
- Core Overview
- Functional Description
- Parameter Settings
- Signals
- Control Register Maps
- 16. Deinterlacer II MegaCore Function
- 17. Frame Reader MegaCore Function
- 18. Frame Buffer MegaCore Function
- 19. Gamma Corrector MegaCore Function
- 20. Interlacer MegaCore Function
- 21. Scaler MegaCore Function
- 22. Scaler II MegaCore Function
- 23. Switch MegaCore Function
- 24. Test Pattern Generator MegaCore Function
- 25. Trace System MegaCore Function
- A. Avalon-ST Video Verification IP Suite
- B. Choosing the Correct Deinterlacer
- Additional Information
10–8 Chapter 10: Clocked Video Input MegaCore Function
Functional Description
Video and Image Processing Suite January 2013 Altera Corporation
User Guide
f Refer to the SMPTE 2016-1-2007 standard for a more detailed description of the AFD
codes.
Table 10–6 lists the AFD Extractor register map.
Stall Behavior and Error Recovery
The stall behavior of the Clocked Video Input MegaCore function is dictated by the
incoming video. If its output FIFO is empty, during horizontal and vertical blanking
periods the Clocked Video Input does not output any video data.
Error Recovery
If an overflow is caused by a downstream core failing to receive data at the rate of the
incoming video, the Clocked Video Input MegaCore function sends an early end of
packet and restart sending video data at the start of the next frame or field.
1 For more information about the stall behavior and error recovery, refer to “Stall
Behavior and Error Recovery” on page 1–3.
Table 10–6. AFD Extractor Register Map
Address Register Description
0 Control
When bit 0 is 0, the core discards all packets.
When bit 0 is 1, the core passes through all non-
ancillary packets.
1 Reserved.
2 Interrupt
When bit 1 is 1, a change to the AFD data has been
detected and the interrupt has been set. Writing a 1 to
bit 1 clears the interrupt.
3 AFD Bits 0-3 contain the active format description code.
4 AR Bit 0 contains the aspect ratio code.
5 Bar data flags
When AFD is 0000 or 0100, bits 0-3 describe the
contents of bar data value 1 and bar data value 2.
When AFD is 0011, bar data value 1 is the pixel number
end of the left bar and bar data value 2 is the pixel
number start of the right bar.
When AFD is 1100, bar data value 1 is the line number
end of top bar and bar data value 2 is the line number
start of bottom bar.
6 Bar data value 1 Bits 0-15 contain bar data value 1
7 Bar data value 2 Bits 0-15 contain bar data value 2
8 AFD valid
When bit 0 is 0, an AFD packet is not present for each
image packet.
When bit 0 is 1, an AFD packet is present for each
image packet.