User guide

10–10 Chapter 10: Clocked Video Input MegaCore Function
Signals
Video and Image Processing Suite January 2013 Altera Corporation
User Guide
Signals
Table 10–9 lists the input and output signals for the Clocked Video Input MegaCore
function.
Interlaced or progressive
Progressive,
Interlaced
Choose the format to be used when no format can be automatically
detected.
Width
32–65,536,
Default = 1920
Choose the image width to be used when no format can be automatically
detected.
Height, Frame / Field 0
32–65,536,
Default = 1080
Choose the image height to be used when no format can be automatically
detected.
Height, Field 1
32–65,536, Default
= 1080
Choose the image height for interlaced field 1when no format can be
automatically detected.
Sync Signals
Embedded in video,
On separate wires
Choose whether the synchronization signal is embedded in the video
stream or provided on a separate wire.
Allow color planes in
sequence input
On or Off
Choose whether run-time switching is allowed between sequential and
parallel color plane transmission formats. The format is controlled by the
vid_hd_sdn signal.
Generate
synchronization outputs
No, Yes, Only
Specifies whether the Avalon-ST output and synchronization outputs (
sof ,
sof_locked , refclk_div ) are generated:
■ No—Only Avalon-ST Video output
■ Yes—Avalon-ST Video output and synchronization outputs
■ Only—Only synchronization outputs
Width of bus “vid_std” 1 - 16 The width, in bits, of the vid_std bus.
Extract ancillary packets On or Off Specifies whether ancillary packets are extracted in embedded sync mode.
Pixel FIFO size
32–(memory limit),
Default = 1920
Choose the required FIFO depth in pixels (limited by the available on-chip
memory).
Video in and out use the
same clock
On or Off
Turn on if you want to use the same signal for the input and output video
image stream clocks.
Use control port On or Off Turn on to use the optional stop/go control port.
Table 10–8. Clocked Video Input Parameter Settings (Part 2 of 2)
Parameter Value Description
Table 10–9. Clocked Video Input Signals (Part 1 of 3)
Signal Direction Description
rst In
The MegaCore function asynchronously resets when you assert
rst . You must
deassert
rst synchronously to the rising edge of the is_clk signal.
vid_clk In Clocked video clock. All the video input signals are synchronous to this clock.
av_address In
control slave port Avalon-MM address bus. Specifies a word offset into the slave
address space.
(1)
av_read In
control slave port Avalon-MM read signal. When you assert this signal, the
control port drives new data onto the read data bus.
(1)
av_readdata Out
control slave port Avalon-MM read data bus. These output lines are used for read
transfers.
(1)
av_write In
control slave port Avalon-MM write signal. When you assert this signal, the
control port accepts new data from the write data bus.
(1)