User guide

Chapter 10: Clocked Video Input MegaCore Function 10–11
Signals
January 2013 Altera Corporation Video and Image Processing Suite
User Guide
av_writedata In
control slave port Avalon-MM write data bus. These input lines are used for write
transfers.
(1)
is_clk In
Clock signal for Avalon-ST ports
dout and control . The MegaCore function
operates on the rising edge of the
is_clk signal.
is_data Out
dout port Avalon-ST data bus. This bus enables the transfer of pixel data out of the
MegaCore function.
is_eop Out
dout port Avalon-ST endofpacket signal. This signal is asserted when the
MegaCore function is ending a frame.
is_ready In
dout port Avalon-ST ready signal. The downstream device asserts this signal when
it is able to receive data.
is_sop Out
dout port Avalon-ST startofpacket signal. This signal is asserted when the
MegaCore function is starting a new frame.
is_valid Out
dout port Avalon-ST valid signal. This signal is asserted when the MegaCore
function outputs data.
overflow Out
Clocked video overflow signal. A signal corresponding to the overflow sticky bit of
the Status register synchronized to vid_clk . This signal is for information only
and no action is required if it is asserted.
(1)
refclk_div Out
A divided down version of
vid_clk (refclk). Setting the Refclk Divider register
to be the number of samples in a line produces a horizontal reference on this signal
that a PLL can use to synchronize its output clock.
sof Out
Start of frame signal. A change of 0 to 1 indicates the start of the video frame as
configured by the SOF registers. Connecting this signal to a Clocked Video Output
MegaCore function allows the function to synchronize its output video to this
signal.
sof_locked Out Start of frame locked signal. When high the sof signal is valid and can be used.
status_update_int Out
control slave port Avalon-MM interrupt signal. When asserted the status registers
of the MegaCore function have been updated and the master must read them to
determine what has occurred.
(1)
vid_data In
Clocked video data bus. This bus enables the transfer of video data into the
MegaCore function.
vid_datavalid In
Clocked video data valid signal. Assert this signal when a valid sample of video data
is present on
vid_data .
vid_f In
(Separate Synchronization Mode Only.) Clocked video field signal. For interlaced
input, this signal distinguishes between field 0 and field 1. For progressive video,
you must deassert this signal.
vid_h_sync In
(Separate Synchronization Mode Only.) Clocked video horizontal synchronization
signal. Assert this signal during the horizontal synchronization period of the video
stream.
vid_hd_sdn In
Clocked video color plane format selection signal (in run-time switching of color
plane transmission formats mode only). This signal distinguishes between
sequential (when low) and parallel (when high) color plane formats.
vid_locked In
Clocked video locked signal. Assert this signal when a stable video stream is
present on the input. Deassert this signal when the video stream is removed.
vid_std In
Video Standard bus. Can be connected to the
rx_std signal of the SDI MegaCore
function (or any other interface) to read from the
Standard register.
Table 10–9. Clocked Video Input Signals (Part 2 of 3)
Signal Direction Description