Datasheet

ManualsBrandsVishay ManualsDiscrete SemiconductorsMOSFET P, -200 V -6.1 A 40 W TO-220

Document Number: 91169 www.vishay.com

S09-0010-Rev. A, 19-Jan-09 1

Power MOSFET

IRFI9640G, SiHFI9640G

Vishay Siliconix

FEATURES

• Isolated Package

• High Voltage Isolation = 2.5 kV

RMS

(t = 60 s;

f = 60 Hz)

• Sink to Lead Creepage Distance = 4.8 mm

• P-Channel

• Dynamic dV/dt Rating

• Low Thermal Resistance

• Lead (Pb)-free Available

DESCRIPTION

Third generation Power MOSFETs from Vishay provide the

designer with the best combination of fast switching,

ruggedized device design, low on-resistance and

cost-effectiveness.

The TO-220 FULLPAK eliminates the need for additional

insulating hardware in commercial-industrial applications.

The molding compound used provides a high isolation

capability and a low thermal resistance between the tab and

external heatsink. This isolation is equivalent to using a 100

micron mica barrier with standard TO-220 product. The

FULLPAK is mounted to a heatsink using a single clip or by

a single screw fixing.

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).

b. V

= - 50 V, starting T

= 25 °C, L = 26 mH, R

= 25 Ω, I

= - 6.1 A (see fig. 12).

c. I

≤ - 11 A, dI/dt ≤ 150 A/µs, V

≤ V

, T

≤ 150 °C.

d. 1.6 mm from case.

PRODUCT SUMMARY

(V) - 200

DS(on)

(Ω)V

= - 10 V 0.50

(Max.) (nC) 44

(nC) 7.1

(nC) 27

Configuration Single

P-Channel MOSFET

TO-220 FULLPAK

Available

RoHS*

COMPLIANT

ORDERING INFORMATION

Package TO-220 FULLPAK

Lead (Pb)-free

IRFI9640GPbF

SiHFI9640G-E3

SnPb

IRFI9640G

SiHFI9640G

ABSOLUTE MAXIMUM RATINGS T

= 25 °C, unless otherwise noted

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage V

- 200

Gate-Source Voltage V

± 20

Continuous Drain Current V

at - 10 V

= 25 °C

- 6.1

= 100 °C - 3.9

Pulsed Drain Current

- 24

Linear Derating Factor 0.32 W/°C

Single Pulse Avalanche Energy

650 mJ

Repetitive Avalanche Current

- 6.1 A

Repetitive Avalanche Energy

4.0 mJ

Maximum Power Dissipation T

= 25 °C P

40 W

Peak Diode Recovery dV/dt

dV/dt - 5.0 V/ns

Operating Junction and Storage Temperature Range T

, T

stg

- 55 to + 150

°C

Soldering Recommendations (Peak Temperature) for 10 s 300

Mounting Torque 6-32 or M3 screw

10 lbf · in

1.1 N · m

* Pb containing terminations are not RoHS compliant, exemptions may apply

Summary of content (8 pages)

PAGE 1
IRFI9640G, SiHFI9640G Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • Isolated Package • High Voltage Isolation = 2.5 kVRMS (t = 60 s; f = 60 Hz) • Sink to Lead Creepage Distance = 4.8 mm • P-Channel • Dynamic dV/dt Rating • Low Thermal Resistance • Lead (Pb)-free Available - 200 RDS(on) (Ω) VGS = - 10 V 0.50 Qg (Max.) (nC) 44 Qgs (nC) 7.
PAGE 2
IRFI9640G, SiHFI9640G Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient RthJA - 65 Maximum Junction-to-Case (Drain) RthJC - 3.1 UNIT °C/W SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS = 0 V, ID = - 250 µA - 200 - - V ΔVDS/TJ Reference to 25 °C, ID = - 1 mA - - 0.22 - V/°C VGS(th) VDS = VGS, ID = - 250 µA - 2.0 - - 4.
PAGE 3
IRFI9640G, SiHFI9640G Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted Fig. 1 - Typical Output Characteristics, TC= 25 °C Fig. 2 - Typical Output Characteristics, TC= 150 °C Document Number: 91169 S09-0010-Rev. A, 19-Jan-09 Fig. 3 - Typical Transfer Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature www.vishay.
PAGE 4
IRFI9640G, SiHFI9640G Vishay Siliconix Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage www.vishay.com 4 Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Maximum Safe Operating Area Document Number: 91169 S09-0010-Rev.
PAGE 5
IRFI9640G, SiHFI9640G Vishay Siliconix RD VDS VGS D.U.T. RG +VDD - 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit td(on) td(off) tf tr VGS 10 % 90 % VDS Fig. 9 - Maximum Drain Current vs. Case Temperature Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case L Vary tp to obtain required IAS IAS VDS D.U.T. RG VDS + V DD VDD IAS tp - 10 V tp 0.01 Ω VDS Fig.
PAGE 6
IRFI9640G, SiHFI9640G Vishay Siliconix Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG - 10 V 12 V 0.2 µF 0.3 µF QGS - QGD D.U.T. VG + VDS VGS - 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform www.vishay.com 6 Fig. 13b - Gate Charge Test Circuit Document Number: 91169 S09-0010-Rev.
PAGE 7
IRFI9640G, SiHFI9640G Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit D.U.T. + Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - RG + • dV/dt controlled by RG • ISD controlled by duty factor "D" • D.U.T. - device under test + - VDD Compliment N-Channel of D.U.T. for driver Driver gate drive P.W. Period D= P.W. Period VGS = - 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T.
PAGE 8
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