Institut für Integrierte Systeme Integrated Systems Laboratory Department of Information Technology and Electrical Engineering VLSI I: From Architectures to VLSI Circuits and FPGAs 227-0116-00L Exercise 3 VHDL Synthesis Prof. Dr. H. Kaeslin Dr. N. Felber SVN Rev.: Last Changed: 1478 13-03-2015 Reminder: With the execution of this training you declare that you understand and accept the regulations about using CAE/CAD software installations at the ETH Zurich.
1 Introduction The VLSI design flow is described in detail in the VLSI textbook. In Figure 1, a very rudimentary overview is given in order to identify the subject of this exercise. Specification Algorithm Design Architecture Design VHDL Coding behavioral VHDL Synthesis Netlist Subject of this exercise Physical Design Chip Layout Netlist Figure 1: VLSI design flow overview.
cp /unspecified/shell.cmd . sh > (a) Unspecified shell command. dvc > dvc > dvc > cp /unix/shell.command . (b) Standard UNIX shell command. cp /this/is/a/design/vision/\ shell.cmd . cp /copy/another.file . dcs > dcs > dcs > (c) Design Vision Console command. cp /this/is/a/design/compiler/\ shell.cmd . cp /copy/another.file . (d) Design Compiler Shell command. Figure 2: Different representations of console commands, used throughout this exercise.
Example I: GUI Guided Training Basically, the S YNOPSYS D ESIGN C OMPILER tools can be subdivided into two major parts: Design Vision: This is the graphical user interface (GUI) on top of the S YNOPSYS D ESIGN C OMPILER. It represents a convenient way to interact with the compiler. Its main windows are illustrated in Figure 4 and explained in Section 4.1 and Section 4.2.
4.2 Design Vision - Console The Design Vision Console provides a facility to enter commands in textual form, this way linking the graphical user-interface to the command line interface (i.e., the DC Shell). Furthermore, all commands entered by mouse buttons are echoed here in correct syntax. The command window also reflects all information displayed by reports and menu windows. Note: Some specialized commands are not available through the graphical user interface.
Note: Although the command compile is still known by the S YNOPSYS D ESIGN C OMPILER, it has been replaced by compile_ultra. During this exercise, you may find the compile command somewhere, but this is for demonstration purposes only. 4.5 The Sample Design Now that you are familiar with the most important synthesis steps, we will explain how to use the S YNOPSYS D ESIGN C OMPILER with the aid of a small sample design. Open the file ./sourcecode/crc4.vhd and have a look at the source.
• Open it using the less programa : sh > less crc4.v The netlist contains a number of logic gates from the standard cell library, interconnected with some wires. Amongst other cells, Table 1 lists those standard cells. Table 1: Some gates of the standard cell library.
5 Example II: Getting to Grips with the Command Line In the first exercise example you have learned what steps are necessary in order to synthesize a design described in VHDL using the Design Vision GUI. Now we will treat the synthesis process more detailed by use of the DC Shell. This gives us the opportunity to create command scripts, which can then be executed multiple times if required. Moreover, we will start to deal with the definition of synthesis constraints. 5.
Student Task 2: • In the following, the first two commands of the synthesis script are listeda . remove_design -designs sh rm -rf WORK/* • Add a short description in the script and explain what these lines are doing b ? • Enter the two commands into the DC Shell and execute them. Note that you can use the mouse in order to copy the respective lines in the Tcl script by simply selecting them with the left mouse button and paste them into the DC shell using the middle mouse button.
Afterwards you can check whether your re-run was successful or not with the check_design command. Beside the S YNOPSYS D ESIGN C OMPILER commands you have inserted into the synthesis script on your own, some already pre-defined commands exist.
COUNT_DP_reg[4] RST_RBI CLK_CI ENA_SI Rst E D Q COUNT_DO[4] COUNT_DP_reg[3] Rst E D Q COUNT_DO[3] COUNT_DP_reg[2] Rst E D Q COUNT_DO[2] COUNT_DP_reg[1] Rst E D Q COUNT_DO[1] COUNT_DP_reg[0] Rst E D Q Figure 6: Block diagram of the Gray Counter example.
6 Example III: Constraining a Circuit In this section, we will go through the synthesis process of a small design step by step and explore different constraints. Try to understand all of the steps – for further explanations and more details please refer to the Synopsys Online Documentation (SOLD), which can be launched using the following UNIX shell command: sh > synopsys-2014.09 sold For the following steps we will use an example circuit that contains sequential cells as well as combinational parts.
6.2 Defining a Clock Period In the above example, no constraints were given and the S YNOPSYS D ESIGN C OMPILER synthesized the design with the minimum possible effort. The synthesis tool is able to extend its efforts to meet the specified timing constraints. Let us have a look at what happens if we constrain the clock period of the circuit3 . Remove the last design and start from scratch. dcs > dcs > dcs > remove_design -all analyze -format vhdl ../sourcecode/datapath.
Student Task 6: Using the report_timing command determine the timing information of the circuit. Which of the timings illustrated in Figure 7 gets actually reported? Which timing gets reported if you do not specify a clock constraint (i.e. the timing information gathered in Section 6.1)? The four different timing paths of Figure 7 shall be investigated in the datapath.vhd circuit. Therefore, we need better specified timing reports.
6.4 Input and Output Timing In the following part we will examine the effect of the input and the output timing. Input Timing: It is clear that the outputs of a circuit are not immediately available after the active clock edge. In our example it takes roughly 0.74 ns for the outputs to appear after the active clock edge. This has to be taken into consideration for the inputs of our circuit as well.
6.5 Setting Input Drivers and Output Load Input Drivers: In the next steps we want to investigate how the driver that drives the inputs of our circuit can affect the overall timing. Until now the S YNOPSYS D ESIGN C OMPILER assumed ideal input signals that have infinitely steep edges. In reality, our inputs are driven by the outputs of some other circuit with limited driving capabilities.
Student Task 13: Now, redo the compilation with the constraints listed in Table 2. Furthermore, keep the previously determined input- and output-delays. For the last two columns of Table 2, you should have a look at the tSO timing reports and write down the type of the gate at the respective output bit. Table 2: Driving cell variations. clock period Specification Driving Cell Load 1.0 ns 1.
Be aware of the fact that the compilation steps will take longer and longer. The compiler has to push all its efforts to the limit for increasing constraints! 7 Example IV: Magnitude Comparator Our final example is located in the source file ./sourcecode/comparator.vhd and is a purely combinational 4-bit magnitude comparator. Student Task 15: • Have a look at the VHDL code. Two binary inputs are compared to each other.
8 Synthesis Hints Throughout this section, some useful hints with regard to synthesis will be given. They may help you during this exercise or during one of your future VLSI projects. 8.1 DesignVision Command echoing The command echoing feature in the GUI is useful to become familiar with the S YNOPSYS D ESIGN C OMPILER command syntax. Use the history command in order to see a list of all previously executed commands. A script file can be generated by history -h > scripts/scriptfile.tcl.
9 Commonly used Synopsys Design Compiler Commands Table 4: A short cheatsheet for the Synopsys Design Compiler.
