Service Manual Model #: VIZIO L37 V, Inc 320A Kalmus Drive Costa Mesa, CA 92626 TEL : +714-668-0588 FAX :+714-668-9099 Top Confidential
Table of Contents CONTENTS PAGE Sections 1. Features 1-1 2. Specifications 2-1 3. On Screen Display 3-1 4. Factory Preset Timings 4-1 5. Pin Assignment 5-1 6. Main Board I/O Connections 6-1 7. Theory of Circuit Operation 7-1 8. Waveforms 8-1 9. Trouble Shooting 9-1 10. Block Diagram 10-1 11. Spare parts list 11-1 12. Complete Parts List 12-1 Appendix 1. Main Board Circuit Diagram 2. Main Board PCB Layout 3.
VINC Service Manual VIZIO L37 COPYRIGHT © 2000 V, INC. ALL RIGHTS RESERVED. IBM and IBM products are registered trademarks of International Business Machines Corporation. Macintosh and Power Macintosh are registered trademarks of Apple Computer, Inc. VINC and VINC products are registered trademarks of V, Inc. VESA, EDID, DPMS and DDC are registered trademarks of Video Electronics Standards Association (VESA). Energy Star is a registered trademark of the US Environmental Protection Agency (EPA).
Chapter 1 Features 1. Built in TV channel selector for TV viewing 2. Simulatnueous display of PC and TV images 3. Connectable to PC’s analog RGB port 4. Built in s-video, HDTV, composite video, HDMI ,TV and DTV out 5. Built in auto adjust function for automatic adjument of screen display 6. Smoothing function enables display of smooth texts and graphics even if image withresolution lower than 1366x768 is magnified 7. Picture In Picture (PIP) funtion to show TV or VCR images 8.
Chapter 2 Specification 1. LCD CHARACTERISTICS Type: WXGA TFT LCD Size: 37 inch Display Size: 37.02 inches (940.3mm) diagonal Outline Dimension: 877.0/878.0 mm (H) x 516.8 mm (V) x 55.5 (D) mm (Typ.) Pixel Pitch: 0.200mm x 0.600mm x RGB Pixel Format: 1366 horiz. By 768 vert. Pixels RGB strip arrangement Contrast ratio: 600(Typ) Luminance, White: 500 cd/m2 (Typ) Display Operating Mode: normally Black Surface Treatment : Hard coating(3H), Anti-glare treatment of the front polarizer Color Depth : 8-bit, 16.
b. Signal Level Video (Y): Analog 0.1Vp-p/75 Video (C): Analog 0.286p-p/75 Sync (H+V): 0.3V below Video (Y) c. Frequency H: 15.734KHz V: 60Hz (NTSC) 3.2.3 F-Type TV RF connector 3.2.3.1 NTSC System: a. Signal Level: Analog 1Vp-p typical(45dB~90dB) b. System :NTSC c. Frequency: 55~801MHz (NTSC) 3.2.3.2 ATSC System a. IF-output level: 1Vp-p minimum b. System: ATSC c. Frequency: 57~863MHz(ATSC) 3.2.4 PC connector 15 pin male D-sub connector a. Pin Assignment : CONFIDENTIAL – DO NOT COPY Page 2-2 File No.
b. Signal Level Video (R, G, B) : Analog 0.7Vp-p/75 Sync (H, V) : TTL level c. Sync Type TTL (Separate / Composite) or Sync. On-Green d. Sync polarity Positive or Negative e. Frequency : H: support to 30K~70KHz V: support to 50~85Hz Pixel Clock: support to 110MHz 3.2.5 HDMI Signal (Digital HD): a. Pin Assignment CONFIDENTIAL – DO NOT COPY Page 2-3 File No.
b. Type: TYPE A c. Polarity: Positive or Negative d. Frequency: H: 15.734KHz V: 60Hz (NTSC-480i) H: 31KHz V: 60Hz (NTSC-480p) H: 45KHz V: 60Hz (NTSC-720p) H: 33KHz V: 60Hz (NTSC-1080i) CONFIDENTIAL – DO NOT COPY Page 2-4 File No.
3.2.6 Component signal (Analog HD1 and Analog HD2) 3.2.6.1 Analog HD1 a. Frequency H: 15.734KHz V: 60Hz (NTSC-480i) H: 31KHz V: 60Hz (NTSC-480p) H: 45KHz V: 60Hz (NTSC-720p) H: 33KHz V: 60Hz (NTSC-1080i) b. Signal level Y: 1Vp-p Pb: ±0.350Vp-p Pr: ±0.350Vp-p c. Impedance 75 3.2.6.2 Analog HD2 a. Frequency H: 15.734KHz V: 60Hz (NTSC-480i) H: 31KHz V: 60Hz (NTSC-480p) H: 45KHz V: 60Hz (NTSC-720p) H: 33KHz V: 60Hz (NTSC-1080i) b. Signal level Y: 1Vp-p Pb: ±0.350Vp-p Pr: ±0.350Vp-p c. Impedance 75 3.2.
8. DIMENSIONS (Physical dimension) Width: 959.9mm. Depth: 311.0mm Height: 748.4mm 9. WEIGHT (Physical weight) a. Net: 25.9kgs b. Gross: 33.5kg 9-1. MOUNTING PRECAUTIONS (1) You must mount a module using holes arranged in four corners or four sides. (2) You should consider the mounting structure so that uneven force (ex. Twisted stress) is not applied to the module. And the case on which a module is mounted should have sufficient strength so that external force is not transmitted directly to the module.
9-2. OPERATING PRECAUTIONS (1) The spike noise causes the mis-operation of circuits. It should be lower than following voltage : V=±200mV(Over and under shoot voltage) (2) Response time depends on the temperature.(In lower temperature, it becomes longer.) (3) Brightness depends on the temperature. (In lower temperature, it becomes lower.) And in lower temperature, response time(required time that brightness is stable after turned on) becomes longer.
Chapter 3 On Screen Display Main unit button Power Input CH ▲ CH ▼ VOL + VOL MUTE / EXIT MENU TV Source A. PICTURE ADJUST： a. PICTURE MODE (USER/ VIVID1 /VIVID2 / VIVID3) b. Adjust the BACKLIGHT (0~100) c. Adjust the BRIGHTNESS (0~100) d. Adjust the CONTRAST (0~100) e. Adjust the COLOR (saturation)(0~100) f. Adjust the TINT (hue) (0~100) g. Adjust the SHARPNESS (0~100) h. CLOSED CAPTION (OFF/CC1/CC2/CC3/CC4/TT1/TT2/TT3/TT4) B. AUDIO ADJUST： a. VOLUME (0~100) b. BASS (0~100) c. TREBLE (0~100) d.
e. SKIP CHANNEL (YES/NO) D. PARENTAL CONTROL： a. PARENT LOCK ENABLE (ON/OFF) b. TV RATING c. MOVIE RATING d. ACCESS CODE EDIT E. PIP SETUP： a. STYLE (OFF/PIP/POP) b. Source (AV1、AV2、AV3、ANALOGHD1、ANALOG HD2、DIGITAL HD RGB、DTV) c. SIZE (SMALL (20%)/MEDIUM (30%)/LARGE (40%)) d. POSITION (TOP LEFT/TOP CENTER/TOP RIGHT/MIDDLE LEFT /MIDDLE RIGHT/BOTTOM LEFT/BOTTOM CENTER/BOTTOM RIGHT) F. SPECIAL FEATURES： a. LANGUAGE (ENGLISH/FRANCE/SPANISH) b. SLEEP TIMER (OFF/30/60/90/120) c.
C. AUDIO ADJUST： a. VOLUME (0~100) b. BASS (0~100) c. TREBLE (0~100) d. BALANCE (0~100) e. SURROUND (ON/OFF) f. REVERB (OFF, CONCERT, LIVING ROOM, HALL, ARENA) g. MUTE (ON/OFF) h. SPEAKERS (ON/OFF) D. PIP SETUP： a. STYLE (OFF/PIP/POP) b. SOURCE (AV1、AV2、AV3、TV) c. SIZE (SMALL (20%)/MEDIUM(30%)/LARGE (40%)) d. POSITION (TOP LEFT/TOP CENTER/TOP RIGHT/MIDDLE LEFT /MIDDLE RIGHT/BOTTOM LEFT/BOTTOM CENTER/BOTTOM RIGHT) E. SPECIAL FEATURES： a. LANGUAGE (ENGLISH/FRANCE/SPANISH) b. SLEEP TIMER (OFF/30/60/90/120) c.
f. REVERB (OFF, CONCERT, LIVING ROOM, HALL, ARENA) g. MUTE (ON/OFF) h. SPEAKERS (ON/OFF) i. AUDIO SOURCE(DIGITAL HD/DTV) C. PARENTAL CONTROL： a. PARENT LOCK ENABLE (ON/OFF) b. TV RATING c. MOVIE RATING d. ACCESS CODE EDIT D. PIP SETUP： a. STYLE (OFF/PIP/POP) b. SOURCE (AV1、AV2、AV3、TV) c. SIZE (SMALL (20%)/MEDIUM (30%)/LARGE (40%)) d. POSITION (TOP LEFT/TOP CENTER/TOP RIGHT/MIDDLE LEFT /MIDDLE RIGHT/BOTTOM LEFT/BOTTOM CENTER/BOTTOM RIGHT) E. SPECIAL FEATURES： a. LANGUAGE (ENGLISH/FRANCE/SPANISH) b.
B. AUDIO ADJUST： a. VOLUME (0~100) b. BASS (0~100) c. TREBLE (0~100) d. BALANCE (0~100) e. SURROUND (ON/OFF) f. REVERB (OFF, CONCERT, LIVING ROOM, HALL, ARENA) g. MUTE (ON/OFF) h. SPEAKERS (ON/OFF) C. PARENTAL CONTROL： a. PARENT LOCK ENABLE (ON/OFF) b. TV RATING c. MOVIE RATING d. ACCESS CODE EDIT D. PIP SETUP： a. STYLE (OFF/PIP/POP) b. SOURCE (AV2、AV3、ANALOGHD1、ANALOG HD2、DIGITAL HD、 RGB、TV) c. SIZE (SMALL (20%)/MEDIUM (30%)/LARGE (40%)) d.
g. Adjust the SHARPNESS (0~100) B. AUDIO ADJUST： a. VOLUME (0~100) b. BASS (0~100) c. TREBLE (0~100) d. BALANCE (0~100) e. SURROUND (ON/OFF) f. REVERB (OFF, CONCERT, LIVING ROOM, HALL, ARENA) g. MUTE (ON/OFF) h. SPEAKERS (ON/OFF) C.DTV OSD a. DTV TUNER SETUP 1. TIME ZONE: α. HAWALL β. EASTTERN TIME γ. INDIANA δ. CENTRAL TIME ε. MOUNTAIN TIME ζ. ARIZONA η. PACIFIC TIME θ. ALASKA 2. AUTO SCAN 3. MANUAL SCAN PRESS (1) ADD-ON MODE (2) RANGE MODE α. FORM CHANNEL(2~69) β. TO CHANNEL(2~69) 4.
2. DIGITAL COLOSED CAPTION α.OFF β.SERVICE1 γ.SERVICE2 δ.SERVICE3 ε.SERVICE4. ζ.SERVICE5 η.SERVICE6 3. DIGITAL CAPTION STYLE PRESS (1) AS BROADCASTER (2)CUSTOM FONT SIZE α.LARGE β.SMALL γ.MEDIUM FONT COLOR α.BLACK β.WHITE γ.GREEN δ.BLUE ε.RED ζ.CYAN η.YELLOW θ.MAGENTA FONT OPACITY α.SOLID β.TRANSLUCENT γ.TRANSPARENT BLACKGROUND COLOR α.BLACK β.WHITE γ.GREEN δ.BLUE ε.RED ζ.CYAN CONFIDENTIAL – DO NOT COPY Page 3-7 File No.
η.YELLOW θ.MAGENTA BLACKGROUND OPACITY α.SOLID β.TRANSLUCENT γ.TRANSPARENT WINDOW COLOR α.BLACK β.WHITE γ.GREEN δ.BLUE ε.RED ζ.CYAN η.YELLOW θ.MAGENTA WINDOW OPACITY α.SOLID β.TRANSLUCENT γ.TRANSPARENT c.PARENTAL CONTROL PASSWORD PRESS 1.0000 2.CHANNEL BLOCK PRESS D. PARENTAL CONTROL： a. PARENT LOCK ENABLE (ON/OFF) b. TV RATING c. MOVIE RATING d. ACCESS CODE EDIT E. PIP SETUP： a. STYLE (OFF/PIP/POP) b. SOURCE (AV1、AV2、AV3、TV) c. SIZE (SMALL (20%)/MEDIUM (30%)/LARGE (40%)) d.
F. SPECIAL FEATURES： a. LANGUAGE (ENGLISH/FRANCE/SPANISH) b. SLEEP TIMER (OFF/30/60/90/120) c. WIDE FORMAT (NORMAL/WIDE) d. RESET ALL SETTING CONFIDENTIAL – DO NOT COPY Page 3-9 File No.
Chapter4 Factory preset timings This timing chart is already preset for the TFT LCD analog & digital display monitors. Refresh Horizontal Vertical Horizontal Vertical Pixel rate Frequency Frequency Polarity Polarity Rate 640x480 60Hz 31.5kHz 59.94Hz N N 25.175 640x480 75Hz 37.5kHz 75.00Hz N N 31.500 800X600 60Hz 37.9kHz 60.317Hz P P 40.000 800x600 75Hz 46.9kHz 75.00Hz P P 49.500 800X600 85Hz 53.7kHz 85.06Hz P P 56.250 1024x768 60Hz 48.4kHz 60.
Chapter5 Pin Assignment The TFT LCD analog display monitors use a 15 Pin Mini D-Sub connector as video input source. Pin Description 1 Red 2 Green 3 Blue 4 Ground 5 Ground 6 R-Ground 7 G-Ground 8 B-Ground 9 +5V for DDC 10 Ground 11 No Connection 12 (SDA) 13 H-Sync (Composite Sync) 14 V-Sync 15 (SCL) Table 1. 1 5 6 11 CONFIDENTIAL – DO NOT COPY 10 15 Page 5-1 File No.
PC connector 15 pin male D-sub connector a. Pin Assignment Refer to Table 1 b. Signal Level Video (R, G, B): Analog 0.7Vp-p/75Ω Sync (H, V): TTL level RGB Signal: a. Sync Type TTL (Separate / Composite) or Sync. On Green b. Sync polarity Positive or Negative c. Video Amplitude RGB: 0.7Vp-p d.
HDMI Signal (Digital HD): a. Pin Assignment Refer to Table 2. b. Type A c. Polarity Positive or Negative d. Frequency H: 15.734KHz V: 60Hz (NTSC-480i) H: 31KHz V: 60Hz (NTSC-480p) H: 45KHz V: 60Hz (NTSC-720p) H: 33KHz V: 60Hz (NTSC-1080i) Four-Pin mini DIN S-Video Connector a. Pin Assignment CONFIDENTIAL – DO NOT COPY Page 5-3 File No.
b. Signal Level Video (Y): Analog 0.1Vp-p/75Ω Video (C): Analog 0.286p-p/75 Sync (H+V): 0.3V below Video (Y) Frequency H: 15.734KHz V: 60Hz (NTSC) CONFIDENTIAL – DO NOT COPY Page 5-4 File No.
F-Type TV RF connector NTSC System: a. Signal Level: Analog 1Vp-p typical(45dB~90dB) b. System :NTSC c. Frequency: 55~801MHz (NTSC) ATSC System a. IF-output level: 1Vp-p minimum b. System: ATSC c. Frequency: 57~863MHz(ATSC) Component signal (Analog HD1 and Analog HD2) Analog HD1 a. Frequency H: 15.734KHz V: 60Hz (NTSC-480i) H: 31KHz V: 60Hz (NTSC-480p) H: 45KHz V: 60Hz (NTSC-720p) H: 33KHz V: 60Hz (NTSC-1080i) b. Signal level Y: 1Vp-p Pb: ±0.350Vp-p Pr: ±0.350Vp-p c.
Analog HD2 a. Frequency H: 15.734KHz V: 60Hz (NTSC-480i) H: 31KHz V: 60Hz (NTSC-480p) H: 45KHz V: 60Hz (NTSC-720p) H: 33KHz V: 60Hz (NTSC-1080i) b. Signal level Y: 1Vp-p Pb: ±0.350Vp-p Pr: ±0.350Vp-p c. Impedance 75Ω RCA-type (Yellow) Composite Video Connector(AV1,AV2,AV3) a. Signal Level Video (Y+C): Analog 1Vp-p/75 Sync (H+V): 0.3V below Video (Y+C) b. Frequency H: 15.734KHz V:60Hz (NTSC) CONFIDENTIAL – DO NOT COPY Page 5-6 File No.
PHONE JACK AUDIO INPUT : a. Signal Level 1Vrms b. Frequency Response 250Hz-20KHz CONFIDENTIAL – DO NOT COPY Page 5-7 File No.
Chapter 6 Block Diagram The TV system block diagram is powered by power board that transforms AC source of 100V~240V AC +/- 10% @ 50/60 HZ into DC 5V & 12V& 24Vsource. The main board receives different types of video signal into the MTK8205 Ic. Afterward, the MTK8205 Ic process the signals control the various functions of the monitor and outputs control signal, video signal and power to the 37” WXGA panel to be displayed. The power send to the panel is first processed by the inverter.
The function of the inverter is to step up the voltage supplied by the main board to the power that is needed to light up the lamps in the panel. Simultaneously, the digital video signals are processed in the panel and the outcome determines the brightness, pixel on/off and the color displayed on the panel. The analog video signals of S-video, YPbPr, TV, PC and A/V all video signals are translated from analog signals into MTK8205 generates the vertical and horizontal timing signals for display device.
Main Board Block Diagram Video Signal RJ11 P11 Audio Signal Communicate Signal 24C02 U17 Control Pin HDMI CON. P1 FFC 50PIN CON. Sil9011 U16 +12V For DTV Signal +5V +3.3V +2.5V 24C02 U18 D_SUB 15PIN P3 KEY BOARD CONN. IR CONN. DDR SDRAM U11,U12 DC/DC FLASH MEMORY U10 DC POWER 12V IN CONN.
Video Board Block Diagram Video Signal Audio Signal Communicate Signal Control Pin I2C Narrow_IF_OP1&OP2 PORT SAW FILTER U7 AGC Amplifiers U8 IF AGC PHILIPS TD1336 U6 I2C Demodulator MT5111 U9 I2C DDR SDRAM U12,U13 FCC 50PIN CON.
Chapter7 Main Board I/o Connections J7 CONNECTION (TOP→BOTTOM) Pin Description 1 “Auto” 2 “Left” 3 “Right” 4 “Down” 5 “Gnd” 6 “Up” 7 “Menu” 8 “Source” 9 “Power” 10 “LED” 11 “IR” 12 “+5V” J1 CONNECTION (TOP→BOTTOM) Pin Description 1 “POWRSW” 2 “+12V” 3 “+12V” 4 “+12V” 5 “GND” 6 “GND” 7 “GND” 8 “GND” 9 “+5V” 10 “+5V” 11 “+5V” 12 “PWM” 13 “BL ON/OFF” CONFIDENTIAL – DO NOT COPY Page 7-1 File No.
J3 CONNECTION (TOP→BOTTOM) Pin Description Pin Description 1 “+3.3V” 16 “HPR” 2 “GND” 17 “HPL” 3 “G/Y” 18 “GNDV” 4 “B/U” 19 “HPDET#” 5 “R/V” 20 “AV3_IN” 6 “LMAIN1” 21 “AV3_GND” 7 “RMAIN1” 22 “AV3L” 8 “+5.0V” 23 “AV3L GND” 9 “GND” 24 “AV3R” 10 “8302IR” 25 “AV3R GND” 11 “8302NET1” 26 “S1Y_IN” 12 “8302NET2” 27 “S1Y_GND” 13 “8302RXD” 28 “S1C_IN” 14 “8302TXD” 29 “S1C_GND” 15 “GNDV” 30 “SVDET2#” CONFIDENTIAL – DO NOT COPY Page 7-2 File No.
J2 CONNECTION (TOP→BOTTOM) Pin Description Pin Description 1 “GND” 26 “GND” 2 “I2C_SW” 27 “VOG3” 3 “OREQUEST#” 28 “VOG2” 4 “OREADY#” 29 “VOG1” 5 “ORESET#” 30 “VOG0” 6 “GND” 31 “GND” 7 “VOPCLK” 32 “VOB7” 8 “VODE” 33 “VOB6” 9 “VOVSYNC” 34 “VOB5” 10 “VOHSYNC” 35 “VOB4” 11 “GND” 36 “GND” 12 “VOR7” 37 “VOB3” 13 “VOR6” 38 “VOB2” 14 “VOR5” 39 “VOB1” 15 “VOR4” 40 “VOB0” 16 “GND” 41 “GND” 17 “VOR3” 42 “AO1SDATA0” 18 “VOR2” 43 “AO1LRCK” 19 “
J8 CONNECTION (TOP→BOTTOM) Pin Description 1 “+5V” 2 “GND” 3 “GND” 4 “+12V” 5 “+12V” CONFIDENTIAL – DO NOT COPY Page 7-4 File No.
Chapter 8 Theory of Circuit Operation The operation of D-SUB 15pin route The D-SUB 15pin is input analog signal to the MTK8205 transfer A/D converter then generates the vertical and horizontal timing signals for display device. The operation of HDMII CON route The HDMI CON is input digital signal the signal is process to the sil9011. Then transfer to the MTK8205, the MTK8205 generates the vertical and horizontal timing signals for display device.
1. The power key through POW and GND to control MTK8205, MTK8205 will receive a low signal to turn on or off system while press the power key. 2. The other key the same as power key . 3. The LED is constructed with two separate LED which color is blue and orange. The MTK8205 direct control the LED’s when MTK8205 (OGO5) is low the LED is orange (Close power) when MTK8205 (OGO5) is high the LED is blue (Open power).
BOLOCK DIAGRAM 1. Video input a. Input Multiplexing 1.component X2 2.composite X3 3.s-videoX1 4.HDMI X1 5.VGA X1 6.RF X2 CONFIDENTIAL – DO NOT COPY Page 8-3 File No.
b. Input formats: 1.support HDTV 480i/480p/720p/1080p 2.support Y/C signal 1VP-P/75Ω 3.support Y/C signal 1VP-P/75Ω 4.support 480i/408p/720p/1080i/1080p 5.support VGA input up to 1366x168@60HZ 6.support NTSC system Frequency 55~801MHZ 7. support ATSC system Frequency 57~863MHZ 2. TV Decoder For pip/pop: Dual identical TVD on chip 3D-comb for both path Dual VBI decoders for the application of V-chip 3. Support Formats: Support NTSC, NTSC-4.
BOLOCK DIAGRAM 4. 2D-Graphic/OSD processor Two OSD planes. Support alpha blending among these two planes and video Support text/bitmap decoder Support line/rectangle/gradient fill Support bitblt Support color key function Support clip mask 65535/256/16/4/2-color bitmap format OSD Automatic vertical scrolling of OSD image Support OSD mirror and upside down CONFIDENTIAL – DO NOT COPY Page 8-5 File No.
5. Microprocessor interface When power is supplied and power key is pressed then the rest circuit lets Reset to low state that will reset the MTK8205 to initial state. After that the Reset will transits to high state and the MTK8205 start to work that microprocessor executes the programs and configures the internal registers. The execution speed of CPU is 133 MHz. a.
b. PIP/POP HARDWARE LIMITION: Secondary Window Source Primary Window Source A B C D E F G H I ATSC Tuner A X 9 9 9 9 X X X X NTSC Tuner B 9 X 9 9 9 9 9 9 9 A/V1 C 9 9 X 9 9 9 9 9 9 A/V2 D 9 9 9 X 9 9 9 9 9 A/V3 (Side) E 9 9 9 9 X 9 9 9 9 Analog HD1 (480i~1080i) F X 9 9 9 9 X X X X Analog HD2 (480i~1080i) G X 9 9 9 9 X X X X Digital HD1 (HDMI) H X 9 9 9 9 X X X X RGB I X 9 9 9 9 X X X X Input Matrix for Windowing Functionality 6. Video processor a.
c. Scaling Arbitrary ratio vertical/horizontal scaling of video, from1/32X to 32X Advanced linear and non-linear Panorama scaling Programmable Zoom viewer Picture in picture (PIP) Picture in picture d. Display 12/10 10/8 8/6 Dithering processing for LCD display 10bit gamma correction Support Alpha blending for Video and two OSD panel Frame rate conversion 7.
8. Flash Usage Flash is used to store FW code, fonts, bitmaps, and big tables for VGA, Video, and Gamma 2Mbyte is recommended to build a general TV model MTK8205 Flash ROM support test report CONFIDENTIAL – DO NOT COPY Page 8-9 File No.
DDR SDRAM (M13S128168A-6T) Application Pin description CONFIDENTIAL – DO NOT COPY Page 8-10 File No.
Command Truth Table 1. Power-Up and Initialization Sequence The following sequence is required for POWER UP and Initialization. 1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.) - Apply VDD before or at the same time as VDDQ. - Apply VDDQ before or at the same time as VTT & VREF). 2. Start clock and maintain stable condition for a minimum of 200us. 3. The minimum of 200us after stable power and clock (CLK, CLK), apply NOP & take CKE high. 4.
6. Issue a mode register set command for “DLL reset”. The additional 200 cycles of clock input is required to lock the DLL.(To issue DLL reset command, provide “High” to A8 and “Low” to BA0) 7. Issue precharge commands for all banks of the device. 8. Issue 2 or more auto-refresh commands. 9. Issue a mode register set command with low to A8 to initialize device operation. 2. Mode Register Set (MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM.
3. Precharge The precharge command is used to precharge or close a bank that has activated. The precharge command is issued when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge each bank respectively or all banks simultaneously. The bank select addresses (BA0, BA1) are used to define which bank is precharged when the command is initiated. For write cycle, tWR(min.) must be satisfied until the precharge command can be issued.
4. Row Active The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock (CLK). The DDR SDRAM has four independent banks; so two Bank Select addresses (BA0, BA1) are required. The Bank Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time (tRCD min). Once a bank has been activated, it must be precharged before another Bank Activation command can be applied to the same bank.
7. Burst Read Operation Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock (CLK) after tRCD from the bank activation. The address inputs determine the starting address for the Burst, The Mode Register sets type of burst. (Sequential or interleave) and burst length (2, 4, 8).
MX29LV160BTTC (Flash) Application The MX29LV800T/B & MX29LV800AT/AB is a 8-mega bit Flash memory organized as 1M bytes of 8 bits or 512K words of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29LV800T/B & MX29LV800AT/AB is packaged in 44-pin SOP, 48-pin TSOP, and 48-ball CSP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers. CONFIDENTIAL – DO NOT COPY Page 8-16 File No.
BLOCK DIAGRAM 1. COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 5 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. CONFIDENTIAL – DO NOT COPY Page 8-17 File No.
2. WRITE COMMANDS/COMMAND SEQUENCES To program data to the device or erase sectors of memory, the system must drive WE and CE to VIL, and OE to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a byte, instead of four. The "byte Program Command Sequence" section has details on programming data to the device using both standard and Unlock Bypass command sequences.
After the system writes the auto select command sequence, the device enters the auto select mode. The system can then read auto select codes from the internal register (which is separate from the memory array) on Q7-Q0. Standard read cycle timings apply in this mode. Refer to the Auto select Mode and Auto select Command Sequence section for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode.
4. READING ARRAY DATA The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Automatic Program or Automatic Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase suspended sectors, the device outputs status data.
MT5111 Application: MT5111 Functional Block Diagram MT5111 is fully integrated single-chip 8-VSB , designed specifically for the digital terrestrial. HDTV receivers . The chip is fully compliant with the ATSC A/53 digital TV standard. MT5111 includes a 10-bit A/D converter , 8-VSB demodulator , TCM(Trellis-Coded Modulation). Decoder . and Reed-Solomon Forward Error Correction decoder . Moreover , an internal controller handles the acquisition and tracking to ensure the best receiving performance .
The carrier frequency offset and symbol timing offset are both estimated and compensated by a fully digital synchronizer . The synchronizer also controls the rate conversion in the digital re-sampling device by estimating the sampling frequency offset . All synchronization in MT5111 are integrated in digital circuits , no external VCXO is required. The equalizer is adopted to cancel the effect of multi-path fading channel during signal propagation in the air .
8 . 25MHZ crystal for clock generation 9 . Full-digital timing recovery , no VCXO is required 10. Full-digital frequency offset recovery with wide acquisition range –1MHZ~+1MHZ 11. Dual digital AGC control for IF and RF respectively 12. MPEG-2 transport stream output in parallel or serial format 13. On-chip error rate estimators for TS packets , TCM decoder , and equalizer 14. EIA/CEA-909 antenna interface 15. Controlled by I2C interface 16. Supports sleep mode to save power consumption 17.
General Feature List : A . Host CPU: 1. ARM 926EJ 2.16K I-Cache and 16K D-Cache 3. 8K Data TCM and 8K instruction 4. JTAG ICE interface 5. Watch Dog timers B . Transport Demuxer : 1. Support 3 independent transport stream inputs 2. Support serial/parallel interface for each transport stream input 3. Support ATSC , DVB , and MPEG2 transport stream inputs. 4. Programmable sync detection. 5. Support DES/3-DES De-scramble. 6. 96 PID filter and 128 section filters. 7. Support TS recording via IEEE1394 interface.
G . Video Processing : 1. Advanced Motion adaptive de-interlace on SDTV resolution. 2. Support clip 3. 3:2/2:2 pull down source detection. 4. Arbitrary ratio vertical/horizontal scaling of video , from 1/15X to 16X. 5. Support Edge preserve. 6. Support horizontal edge enhancement. 7. Support Quad-Picture. H . Main Display : 1. Mixing two video and three OSD and hardware cursor. 2. Contrast/Brightness adjustment. 3. Gamma correction. 4. Picture-in-Picture( PIP ). 5. Picture-Out-Picture( POP ). 6.
M . Peripheral Bus Interface : 1. Support NOR/NAND flash. 2. Support CableCard host control bus. N . Audio : 1. Support Dolby Digital AC-3 decoding. 2. MPEG-1 layer I/II , MP3 decoding. 3. Dolby prologic II. 4. Main audio output : 5.1ch + 2ch ( down mix ) 5. Auxiliary audio output : 2ch. 6. Pink noise and white noise generator. 7. Equalizer. 8. Bass management. 9. 3D surround processing include virtual surround. 10. Audio and video lip synchronization. 11. Support reverberation. 12. SPDIF out. 13. I2S I/F.
MX29LV320BTTC (Flash) Application : The MX29LV320AT/B is a 32-mega bit Flash memory organized as 4M bytes of 8 bits and 2M words of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29LV320AT/B is packaged in 48-pin TSOP and 48-ball CSP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers.
CONFIDENTIAL – DO NOT COPY Page 8-28 File No.
BLOCK DIAGRAM CONFIDENTIAL – DO NOT COPY Page 8-29 File No.
BUS OPERATION--1 Legend: L=Logic LOW=VIL, H=Logic High=VIH, VID=12.0 0.5V, VHH=11.5-12.5V, X=Don't Care, AIN=Address IN, DIN=Data IN,DOUT=Data OUT Notes: 1. When the WP/ACC pin is at VHH, the device enters the accelerated program mode. See "Accelerated Program Operations" for more information. 2.The sector group protect and chip unprotect functions may also be implemented via programming equipment. See the "Sector Group Protection and Chip Unprotection" section. 3.
BUS OPERATION--2 Notes: 1.Code=00h means unprotected, or code=01h protected. 2.Code=99 means factory locked, or code=19h not factory locked. WRITE COMMANDS/COMMAND SEQUENCES To program data to the device or erase sectors of memory , the system must drive WE and CE to VIL, and OE to VIH. An erase operation can erase one sector, multiple sectors , or the entire device. A "sector address" consists of the address bits required to uniquely select a sector.
TABLE A. MX29LV320AT/B COMMAND DEFINITIONS Legend: X=Don't care RA=Address of the memory location to be read. RD=Data read from location RA during read operation. PA=Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE or CE pulse. PD=Data to be programmed at location PA. Data is latched on the rising edge of WE or CE pulse. SA=Address of the sector to be erased or verified. Address bits A20-A12 uniquely select any sector.
STANDBY MODE MX29LV320AT/B can be set into Standby mode with two different approaches. One is using both CE and RESET pins and the other one is using RESET pin only. When using both pins of CE and RESET, a CMOS Standby mode is achieved with both pins held at Vcc ±0.3V. Under this condition, the current consumed is less than 0.2uA (typ.). If both of the CE and RESET are held at VIH, but not within the range of VCC ± 0.3V, the device will still be in the standby mode, but the standby current will be larger.
The system can thus monitor RY/BY to determine whether the reset operation is complete. If RESET is asserted when a program or erase operation is not executing (RY/BY pin is "1"), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET pin returns to VIH. Refer to the AC Characteristics tables for RESET parameters and to Figure 14 for the timing diagram.
Table B. Write Operation Status Notes: 1. Performing successive read operations from the erase-suspended sector will cause Q2 to toggle. 2. Performing successive read operations from any address will cause Q6 to toggle. 3. Reading the byte/word address being programmed while in the erase-suspend program mode will indicate logic "1" at the Q2 bit. However, successive reads from the erase-suspended sector will cause Q2 to toggle. Fig C. COMMAND WRITE OPERATION CONFIDENTIAL – DO NOT COPY Page 8-35 File No.
Fig D. READ TIMING WAVEFORMS CONFIDENTIAL – DO NOT COPY Page 8-36 File No.
Fig E. RESET TIMING WAVEFORM CONFIDENTIAL – DO NOT COPY Page 8-37 File No.
DDR SDRAM (NT5DS16M16CS-5T) Application : Functional Description The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268, 435, 456 bits. The 256Mb DDR SDRAM is internally configured as a quad-bank DRAM. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins.
Block Diagram (16Mb x 16) Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals. CONFIDENTIAL – DO NOT COPY Page 8-39 File No.
Pin Configuration - 400mil TSOP II (x4 / x8 / x16) CONFIDENTIAL – DO NOT COPY Page 8-40 File No.
Mode Register Operation Operating Mode The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode Register Set command issued to reset the DLL should always be followed by a Mode Register Set command to select normal operating mode.
Extended Mode Register The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, bit A0; output drive strength selection, bit A1; and QFC output enable/disable, bit A2 (NTC optional). These functions are controlled via the bit settings shown in the Extended Mode Register Definition.
Truth Table a: Commands 1. CKE is high for all commands shown except Self Refresh. 2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects ,Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode Register.) 3. BA0-BA1 provide bank address and A0-A12 provide row address. 4.
Write The Write command is used to initiate a burst write access to an active (open) row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8; where [i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether or not Auto Precharge is used.
Operations : Reads Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are initiated with a Read command. The starting column and bank addresses are provided with the Read command and Auto Precharge is either enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is accessed starts precharge at the completion of the burst, provided tRAS has been satisfied.
Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8) CONFIDENTIAL – DO NOT COPY Page 8-46 File No.
Read Command Writes Write bursts are initiated with a Write command, as shown in timing figure Write Command on following: The starting column and bank addresses are provided with the Write command, and Auto Precharge is either enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic Write commands used in the following illustrations, Auto Precharge is disabled.
Data for any Write burst may be concatenated with or truncated with a subsequent Write command. In either case, a continuous flow of input data can be maintained. The new Write command can be issued on any positive edge of clock following the previous Write command. The first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated.
Data Input (Write) Data Output (Read) WM8776 Application The WM8776 is a high performance, stereo audio codec with five channel input selector. The WM8776 is ideal for surround sound processing applications for home hi-fi, DVD-RW and other audiovisual equipment. Etch ADC channel has programmable gain control with automatic level control. Digital audio output word lengths from 16-32 bits and sampling rates from 32kHZ to 96KHZ are supported.
BLOCK DIAGRAM 1. Audio sample rate The master clock forWM8776 supports DAC and ADC audio sampling rates 256fs to 768fs, where fs is the audio sample frequency (DACLRC or ADCLRC) typically 32KHZ, 44.1KHZ, 48KHZ or 96KHZ (the DAC also supports operation at 128fs and 192fs and 192KHZ sample rate). The master clock is used to operate the digital filters and the noise shaping circuits.
2. DIGITAL AUDIO INTERFACE a. Slave mode The audio interfaces operations in either slave mode selectable using the MS control bit. In slave mode DIN is always an input to the WM8776 and DOUT is always an output. The default is Slave mode. In slave mode (ms=0) ADCLRC, DACLRC, ADCBCLK, DACBCLK are input to the WM8776 . DIN and DACLRC are sampled by the WM8776 on the rising edge of DACBCLK; ADCLRC is sampled on the rising edge of ADCBCLK. ADC data is output on DOUT and changes on the falling edge of ADCBCLK.
b. 2 Wire serial control mode The wm8776 supports software control via a 2-wire serial bus. Many devices can be controlled by the same bus, and each device has a uni ue 7-bit address (this is not the same as the 7-bit address of each register in the wm8776). The wm8776 operates as a slave device only. 2-wire serial interface as shown in the following figure. The wm8776 has two possible device addresses, which can be selected using the CE pin In the L37 LCD TV CE pin is LOW (device address is 34h).
Sil9011 Application The sil9011 provides a complete solution for receiving HDMI compliant digital audio and video. Specialized audio and video processing is available within the sil9011 to easily and cost effectively adds HDMI capability to consumer electronics devices such as digital TVs, plasma displays, LCD TVs and projectors. BLOCK DIAGRAM CONFIDENTIAL – DO NOT COPY Page 8-53 File No.
1. TMDS Digital Core The core performs 10-to-8-bit TMDS decoding on the audio and video received from the three TMDS differential data lines along with a TMDS differential clock. The TMDS core supports link clock rates to 165MHZ, including CE modes to 720P/1080I/1080P. 2. Active port detection The Pane Link core detects an active TMDS clock and actively toggling DE signal.
The receiver can also process the video data before it is output as show below figure 5. I2c Interface to Display Controller The Controller I2c interface (CSDA, CSCL) on the sil9011 is a slave interface capable of running up to 400KHZ. This bus is used to configure the SIL9011 by reading/writing to the appropriate registers. The SIL9011 is accessible on the local I2c bits at two-device address.
BLOCK DIAGRAM 1. I2c Bus I2C BUS is interring bus system controlled by 2 lines (SDA, SCL). Data are transmitted and received in the units of byte and Acknowledge. It is transmitted by MSB first from the Start conditions. The data format is set as shown in the following figure. In the L32 TV MM1492 slave address, ADR terminal is L, and 90H is selected. The following figure indicates the control contents of control registers and switches. CONFIDENTIAL – DO NOT COPY Page 8-56 File No.
2. Switch control table a. Video output 1 b. Audio output 1 c. Audio gain CONFIDENTIAL – DO NOT COPY Page 8-57 File No.
TDA8946 Application In L32 TV the TDA8946AJ is a dual-channel audio power amplifier with DC gain control. It has an output power of 2 × 10 W at an 8 Ω load and a 12 V supply. Block diagram 1. Input configuration The TDA8946AJ inputs can be driven symmetrical (floating) as well as asymmetrical. In the asymmetrical mode one input pin is connected via a capacitor to the signal source and the other input is connected to the signal ground.
2. Output power measurement The output power as a function of the supply voltage is measured on the output pins at THD = 10%,in the L32 LCD TV Vcc=12V so we can see as shown in the following figure output about 7W. CONFIDENTIAL – DO NOT COPY Page 8-59 File No.
3. Mode selection In the L32 LCD TV TDA8946AJ has two functional modes, which can be selected by applying the proper DC voltage to pin MODE. a. Mute — In this mode the amplifier is DC-biased but not operational (no audio output). This allows the input coupling capacitors to be charged to avoid pop-noise. The device is in mute mode when 3.5 V < VMODE < (VCC − 1.5 V). b. Operating — In this mode the amplifier is operating normally. The operating mode is activated at VMODE<1.0V.
Chapter 9 Waveforms 1. PC MODE(1366X768 60HZ) CH1 H-sync (FB46); CH2 V-sync (FB45) GREEN (R194) CONFIDENTIAL – DO NOT COPY Page 9-1 File No.
CH1 VGAHSYNC# (FB46); CH2 VGAVSYNC# (FB45) CH1 VGAVSYNC# (FB45); CH2 GREEN (R194) CONFIDENTIAL – DO NOT COPY Page 9-2 File No.
CH1 VGAL (CE81); CH2 AVOL (R252) CH1 AUSPL (RA12) ; CH2 L+ (UA1 PIN17) CONFIDENTIAL – DO NOT COPY Page 9-3 File No.
CH1 XTALI (U9 PIN A15);CH2 XTALO (U9 PIN B15) 2. AV&TV MODE (AV1/AV2/AV3/TV) VIDEO CH1 (R88); CH2 (Q4 PIN1) CONFIDENTIAL – DO NOT COPY Page 9-4 File No.
CH1 CVBS1+ (U9 PINA2); CH2 CVBS1 (R136) CH1 AV1L (U20 PIN1); CH2 AUO1L_SWO (U20 PIN36) CONFIDENTIAL – DO NOT COPY Page 9-5 File No.
CH1 AUSPL (RA12) ; CH2 L+ (UA1 PIN17) CH1 D_CLK# (U11 PIN46);CH2 D_DQ15(U11 PIN65) CONFIDENTIAL – DO NOT COPY Page 9-6 File No.
CH1 DACMCLK (U22 PIN11);CH2 DOUT (U22 PIN12) CH1 SCL34H(U22 PIN19);CH2 SDA34H (U22 PIN18) CONFIDENTIAL – DO NOT COPY Page 9-7 File No.
3. ANALOG HD MODE (ANALOG HD1/HD2) CH1Y1_IN (R105); CH2 Y (U21 PIN7) CH1Y (R280); CH2 Y+ (C120) CONFIDENTIAL – DO NOT COPY Page 9-8 File No.
CH1 TUL (U20 PIN44); CH2 AUO1L_SWO (U20 PIN 36) CH1 AUSPL (RA12) ; CH2 L+ (UA1 PIN17) CONFIDENTIAL – DO NOT COPY Page 9-9 File No.
4. DIGITAL HD CH1 DATA2+ (P1 PIN 1); CH2 DATA2- (P1 PIN3) CH1 HDMI0 (U16 PIN 124) ;CH2 HDMI15 (U16 PIN 102) CONFIDENTIAL – DO NOT COPY Page 9-10 File No.
CH1 XTLI (U16 PIN85) ;CH2 XTLO (U16 PIN86) CH1 HDMISDA (U16 PIN39);CH2 HDMISCL (U16 PIN40) CONFIDENTIAL – DO NOT COPY Page 9-11 File No.
DTV Mode(Video Board): CH1 AO1BCK (J1 Pin 7) ; CH2 AO1SDATA0 (J1 PIN 9) CH1 VOPCLK (J1 Pin 44) ; CH2 VOB0 (J1 PIN 11) CONFIDENTIAL – DO NOT COPY Page 9-12 File No.
CH1 VOPCLK (J1 Pin 44) ; CH2 VOG0 (J1 PIN 21) CH1 VOPCLK (J1 Pin 44) ; CH2 VOR0 (J1 PIN 31) CONFIDENTIAL – DO NOT COPY Page 9-13 File No.
CH1 XTAL1 (C63) ; CH2 XTAL2 (C62) CH1 OPWM0 (R42) ; CH2 OXTALI (R43) CONFIDENTIAL – DO NOT COPY Page 9-14 File No.
5. POWER ON/OFF CH1 DV120B (F1); CH2 GPIO (R3); POWER ON CONFIDENTIAL – DO NOT COPY Page 9-15 File No.
CH1 DV120B (F1); CH2 GPIO (R3); POWER OFF CH1 DV50B (U7 PIN8); CH2 GPIO (R3); POWER ON CONFIDENTIAL – DO NOT COPY Page 9-16 File No.
CH1 DV50B (U7 PIN8); CH2 GPIO (R3); POWER OFF CH1 DV120B (U6 PIN1); CH2 AV_V90 (U6 PIN3) POWER ON CONFIDENTIAL – DO NOT COPY Page 9-17 File No.
CH1 DV120B (U6 PIN1); CH2 AV_V90 (U6 PIN3) POWER OFF CH1 DV50A (U4 PIN1); CH2 DV33A (F3) AC POWER ON CONFIDENTIAL – DO NOT COPY Page 9-18 File No.
CH1 DV50A (U4 PIN1); CH2 DV33A (F3) AC POWER OFF CH1 DV33A (U5 PIN 1); CH2 DV18A (U5 PIN2) AC POWER ON CONFIDENTIAL – DO NOT COPY Page 9-19 File No.
CH1 DV33A (U5 PIN 1); CH2 DV18A (U5 PIN2) AC POWER OFF CH1 DV50B(U14 PIN 3); CH2 DV25 (U14 PIN2) POWER ON CONFIDENTIAL – DO NOT COPY Page 9-20 File No.
CH1 DV25 (U13 PIN7); CH2 D1V25 (U13 PIN3) POWER OFF CH1 GPIO (R3); CH2 LVDS-SEQ (R10) POWER ON CONFIDENTIAL – DO NOT COPY Page 9-21 File No.
CH1 GPIO (R3); CH2 LVDS-SEQ (R10) POWER OFF CH1 GPIO (R3); CH2 ATSC-SW(R121) POWER ON CONFIDENTIAL – DO NOT COPY Page 9-22 File No.
CH1 GPIO (R3); CH2 ATSC-SW(R121) POWER OFF CONFIDENTIAL – DO NOT COPY Page 9-23 File No.
Chapter 10 Trouble shooting MONITOR DISPLAY NOTHING (PC MODE) Start N0 LED is lighted 1. 2. 3. 4. Is Power board output +5V? Is J1 connector good? Is DC-DC OK? Is U4 (3.3V) working ok? Yes N0 LED is lighting? It is in power saving 1. Check video cable 2. Is the timing supported? 3. Check sync input 4. Check VGASOG rout if analog (SOG) Yes N0 Is backlight on? 1.Check J1 PIN 1 2.Is inverter ok? Yes Yes N0 U9 no data out? It means data to LVDS 1.Is J6 connecting well? 2.Check J1 +5V&+12V 3.
(TV, COMPOSITE VIDEO1, 2, 3, S-VIDEO) IS NOT DISPLAY CORRECTLY Start N0 1.Check video 2.Check DVD player Input signal good? Yes N0 1.Check P2 signal 2.Check signal between P2 and U20 (IF AV1/AV2 mode) 3.Check Tuner &U20 (IF TV mode) 4.Check J4&J6 (IF AV3&S-Video) 5.Check U20 POWER +9V 6.Check U22 data input/output U20 input correct? Yes N0 1.Check signal between U20 and U9 U20 output correct? Yes N0 LVDS output correct? 1.Check signal between U20 and U9 2.Check U9 clock (27MHz) 3.
(COMPONENT1, 2) IS NOT DISPLAY CORRECTLY Start N0 1.Check video 2.Check host’s setting Input signal good? Yes N0 1.Check signal between P8&U21 2.Check U21 power 3.3V U21 input correct? Yes N0 1.Check signal between U21&U9 2.Check U9 Clock (27MHZ) U9 input correct? Yes N0 LVDS output correct ? 1.Check U9 2.Check U9 power 3.3V 1.8V Yes 1.Is J6 connected good? 2.Is panel working ok? END CONFIDENTIAL – DO NOT COPY Page 10-3 File No.
(HDMI) IS NOT DISPLAY CORRECTLY Start N0 1.Check video 2.Check host’s setting Input signal good? Yes N0 1.Check p1 connect 2.Check signal between P1 and U16 U16 input correct? Yes N0 U16 no data out ? 1.Check U16 power 2.Check between signal U16 and U9 3.Check clock 28.224MHZ Yes 1.Is J6 connected good? 2.Is panel working ok? END CONFIDENTIAL – DO NOT COPY Page 10-4 File No.
TROUBLE OF DC-DC CONVERTER Start N0 J1 PIN 9,10,11 The voltage is about + 5V 1.Check power board 2.Check power cable connection J1 N0 The voltage is about + 12V while power switch on 1.J1 connection good 2.Check U9 GPIO Pin 3.Check power board Yes J1 PIN 2,3,4,5 Yes N0 Yes N0 U7 pin 5 6 7 8 U4 pin2 The voltage is about +5V while power switch on 1.J1 connection good 2. Check U9 GPIO Pin The voltage is about +3.3V 1.J1 to connection good? 2.
TROUBLE OF DDC READING Start N0 Support DDC1/2B 1.Analog cable ok? 2.Check signal (U18 to P3) 3.Check U18 Voltage 4.Is compliant protocol? Analog DDC OK? Yes N0 HDMIDDC OK? Support DDC1/2B 1.Analog cable ok? 2.Check signal (U17 to P1) 3.Check U17 Voltage 4.Is compliant protocol? Yes END CONFIDENTIAL – DO NOT COPY Page 10-6 File No.
