Specifications
VLSI
Solution
y
VS1053b
VS1053B
5. PACKAGES AND PIN DESCRIPTIONS
Pad Name LQFP
Pin
Pin
Type
Function
MICP / LINE1 1 AI Positive differential mic input, self-biasing / Line-in 1
MICN 2 AI Negative differential mic input, self-biasing
XRESET 3 DI Active low asynchronous reset, schmitt-trigger input
DGND0 4 DGND Core & I/O ground
CVDD0 5 CPWR Core power supply
IOVDD0 6 IOPWR I/O power supply
CVDD1 7 CPWR Core power supply
DREQ 8 DO Data request, input bus
GPIO2 / DCLK
1
9 DIO General purpose IO 2 / serial input data bus clock
GPIO3 / SDATA
1
10 DIO General purpose IO 3 / serial data input
GPIO6 / I2S SCLK
3
11 DIO General purpose IO 6 / I2S SCLK
GPIO7 / I2S SDATA
3
12 DIO General purpose IO 7 / I2S SDATA
XDCS / BSYNC
1
13 DI Data chip select / byte sync
IOVDD1 14 IOPWR I/O power supply
VCO 15 DO For testing only (Clock VCO output)
DGND1 16 DGND Core & I/O ground
XTALO 17 AO Crystal output
XTALI 18 AI Crystal input
IOVDD2 19 IOPWR I/O power supply
DGND2 20 DGND Core & I/O ground
DGND3 21 DGND Core & I/O ground
DGND4 22 DGND Core & I/O ground
XCS 23 DI Chip select input (active low)
CVDD2 24 CPWR Core power supply
GPIO5 / I2S MCLK
3
25 DIO General purpose IO 5 / I2S MCLK
RX 26 DI UART receive, connect to IOVDD if not used
TX 27 DO UART transmit
SCLK 28 DI Clock for serial bus
SI 29 DI Serial input
SO 30 DO3 Serial output
CVDD3 31 CPWR Core power supply
XTEST 32 DI Reserved for test, connect to IOVDD
GPIO0 33 DIO Gen. purp. IO 0 (SPIBOOT), use 100 kΩ pull-down resistor
2
GPIO1 34 DIO General purpose IO 1
GND 35 DGND I/O Ground
GPIO4 / I2S LROUT
3
36 DIO General purpose IO 4 / I2S LROUT
AGND0 37 APWR Analog ground, low-noise reference
AVDD0 38 APWR Analog power supply
RIGHT 39 AO Right channel output
AGND1 40 APWR Analog ground
AGND2 41 APWR Analog ground
GBUF 42 AO Common buffer for headphones, do NOT connect to ground!
AVDD1 43 APWR Analog power supply
RCAP 44 AIO Filtering capacitance for reference
AVDD2 45 APWR Analog power supply
LEFT 46 AO Left channel output
AGND3 47 APWR Analog ground
LINE2 48 AI Line-in 2 (right channel)
1
First pin function is active in New Mode, latter in Compatibility Mode.
2
Unless pull-down resistor is used, SPI Boot is tried. See Chapter 9.9 for details.
3
If I2S CF ENA is ’0’ the pins are used for GPIO. See Chapter 10.13 for details.
Version 1.01, 2008-05-22 14