Specifications

VLSI
Solution
y
VS1053b
VS1053B
7. SPI BUSES
7.6 SPI Timing Diagram
XCS
SCK
SI
SO
0 1 1514 16
tXCSS
tXCSH
tWL tWH
tH
tSU
tV
tZ
tDIS
tXCS
30
31
Figure 9: SPI Timing Diagram.
Symbol Min Max Unit
tXCSS 5 ns
tSU 0 ns
tH 2 CLKI cycles
tZ 0 ns
tWL 2 CLKI cycles
tWH 2 CLKI cycles
tV 2 (+ 25 ns
1
) CLKI cycles
tXCSH 1 CLKI cycles
tXCS 2 CLKI cycles
tDIS 10 ns
1
25 ns is when pin loaded with 100 pF capacitance. The time is shorter with lower capacitance.
Note: Although the timing is derived from the internal clock CLKI, the system always starts up in 1.0×
mode, thus CLKI=XTALI. After you have configured a higher clock through SCI CLOCKF and waited
for DREQ to rise, you can use a higher SPI speed as well.
Note: Because tWL + tWH + tH is 6×CLKI + 25 ns, the maximum speed for SCI reads is CLKI/7.
Version 1.01, 2008-05-22 23