Specifications

VLSI

Solution

VS1053b

VS1053B

9. OPERATION

9.12.3 SCI Test

Sci test is initialized with the 8-byte sequence 0x53 0x70 0xEE n 0 0 0 0, where n − 48 is the register

number to test. The content of the given register is read and copied to SCI HDAT0. If the register to be

tested is HDAT0, the result is copied to SCI HDAT1.

Example: if n is 48, contents of SCI register 0 (SCI MODE) is copied to SCI HDAT0.

9.12.4 Memory Test

Memory test mode is initialized with the 8-byte sequence 0x4D 0xEA 0x6D 0x54 0 0 0 0. After this

sequence, wait for 1100000 clock cycles. The result can be read from the SCI register SCI HDAT0, and

’one’ bits are interpreted as follows:

Bit(s) Mask Meaning

15 0x8000 Test ﬁnished

14:10 Unused

9 0x0200 Mux test succeeded

8 0x0100 Good MAC RAM

7 0x0080 Good I RAM

6 0x0040 Good Y RAM

5 0x0020 Good X RAM

4 0x0010 Good I ROM 1

3 0x0008 Good I ROM 2

2 0x0004 Good Y ROM

1 0x0002 Good X ROM 1

0 0x0001 Good X ROM 2

0x83ff All ok

Memory tests overwrite the current contents of the RAM memories.

9.12.5 New Sine and Sweep Tests

A more frequency-accurate sine test can be started and controlled from SCI. SCI AICTRL0 and SCI AICTRL1

set the sine frequencies for left and right channel, respectively. These registers, volume (SCI VOL), and

samplerate (SCI AUDATA) can be set before or during the test. Write 0x4020 to SCI AIADDR to start

the test.

SCI AICTRLn can be calculated from the desired frequency and DAC samplerate by:

SCI AICT RLn = F

sin

× 65536/F

The maximum value for SCI AICTRLn is 0x8000U. For the best S/N ratio for the generated sine, three

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